ATTINY48-AUR Atmel, ATTINY48-AUR Datasheet - Page 55

• Manufacturer Part Number: ATTINY48-AUR
• Description: MCU AVR 4KB FLASH 12MHZ 32TQFP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY48-AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.3
9.3.1
8008G–AVR–04/11
Register Description
EICRA – External Interrupt Control Register A
rupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described
in
If the low level on the interrupt pin is removed before the device has woken up then program
execution will not be diverted to the interrupt service routine but continue from the instruction fol-
lowing the SLEEP command.
The External Interrupt Control Register A contains control bits for interrupt sense control.
• Bits 7:4 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bits 3:2 – ISC1[1:0]: Interrupt Sense Control 1 Bit 1 and Bit 0
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT1 pin that activate the
interrupt are defined in
If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate
an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is
selected, the low level must be held until the completion of the currently executing instruction to
generate an interrupt.
Table 9-2.
• Bits 1:0 – ISC0[1:0]: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined in
If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate
an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is
Bit
(0x69)
Read/Write
Initial Value
Table 6-5 on page
ISC11
0
0
1
1
Interrupt 1 Sense Control
ISC10
R
7
–
0
0
1
0
1
33.
Table
Table
Description
The low level of INT1 generates an interrupt request.
Any logical change on INT1 generates an interrupt request.
The falling edge of INT1 generates an interrupt request.
The rising edge of INT1 generates an interrupt request.
R
6
–
0
9-2. The value on the INT1 pin is sampled before detecting edges.
9-3. The value on the INT0 pin is sampled before detecting edges.
R
5
–
0
R
4
–
0
ISC11
R/W
3
0
ISC10
R/W
2
0
ISC01
R/W
1
0
ATtiny48/88
ISC00
R/W
0
0
EICRA
55