ATTINY48-AUR Atmel, ATTINY48-AUR Datasheet - Page 114
ATTINY48-AUR
Manufacturer Part Number
ATTINY48-AUR
Description
MCU AVR 4KB FLASH 12MHZ 32TQFP
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY48-MU.pdf
(302 pages)
Specifications of ATTINY48-AUR
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
28
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
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Manufacturer:
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Quantity:
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12.11.5
12.11.6
12.11.7
12.11.8
114
ATtiny48/88
OCR1AH and OCR1AL – Output Compare Register 1 A
OCR1BH and OCR1BL – Output Compare Register 1 B
ICR1H and ICR1L – Input Capture Register 1
TIMSK1 – Timer/Counter1 Interrupt Mask Register
Writing to the TCNT1 Register blocks (removes) the compare match on the following timer clock
for all compare units.
The Output Compare Registers contain a 16-bit value that is continuously compared with the
counter value (TCNT1). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC1x pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are
written simultaneously when the CPU writes to these registers, the access is performed using an
8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other
16-bit registers.
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the
ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit
registers.
• Bits 7:6 – Res: Reserved Bits
These bits are reserved and will always read zero.
Bit
(0x89)
(0x88)
Read/Write
Initial Value
Bit
(0x8B)
(0x8A)
Read/Write
Initial Value
Bit
(0x87)
(0x86)
Read/Write
Initial Value
Bit
(0x6F)
Read/Write
Initial Value
See “Accessing 16-bit Registers” on page 91.
See “Accessing 16-bit Registers” on page 91.
R/W
R/W
R/W
R
7
0
7
0
7
0
7
–
0
R/W
R/W
R/W
R
6
–
0
6
0
6
0
6
0
ICIE1
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
R/W
R/W
R/W
R
4
–
0
4
OCR1A[15:8]
0
4
OCR1B[15:8]
0
4
0
OCR1A[7:0]
OCR1B[7:0]
ICR1[15:8]
ICR1[7:0]
R/W
R/W
R/W
R
3
–
0
3
0
3
0
3
0
OCIE1B
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
OCIE1A
R/W
R/W
R/W
R/W
1
0
1
0
1
0
1
0
TOIE1
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
8008G–AVR–04/11
OCR1AH
OCR1AL
OCR1BH
OCR1BL
TIMSK1
ICR1H
ICR1L
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