ATTINY48-AUR Atmel, ATTINY48-AUR Datasheet - Page 127
ATTINY48-AUR
Manufacturer Part Number
ATTINY48-AUR
Description
MCU AVR 4KB FLASH 12MHZ 32TQFP
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY48-MU.pdf
(302 pages)
Specifications of ATTINY48-AUR
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
28
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY48-AUR
Manufacturer:
Atmel
Quantity:
5 975
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14.5.2
8008G–AVR–04/11
SPSR – SPI Status Register
• Bit 2 – CPHA: Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or
trailing (last) edge of SCK. Refer to
functionality is summarized below:
Table 14-4.
• Bits 1:0 – SPR[1:0]: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have
no effect on the Slave. The relationship between SCK and the oscillator clock frequency f
shown in the following table:
Table 14-5.
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in
SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is
in Master mode, this will also set the SPIF Flag. SPIF is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the
SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).
• Bit 6 – WCOL: Write COLlision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The
WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set,
and then accessing the SPI Data Register.
• Bits 5:1 – Res: Reserved Bits
These bits are reserved and will always read zero.
Bit
0x2D (0x4D)
Read/Write
Initial Value
SPI2X
0
0
0
0
1
1
1
1
CPHA
CPHA Functionality
Relationship Between SCK and the Oscillator Frequency
0
1
SPIF
R
7
0
WCOL
SPR1
R
6
0
0
0
1
1
0
0
1
1
R
5
–
0
Figure 14-3
Leading Edge
Sample
Setup
SPR0
R
4
–
0
0
1
0
1
0
1
0
1
and
R
3
–
0
Figure 14-4
SCK Frequency
f
f
f
f
f
f
f
f
osc
osc
osc
osc
osc
osc
osc
osc
/
/
/
/
/
/
/
/
4
16
64
128
2
8
32
64
R
2
–
0
for an example. The CPOL
R
1
–
0
Trailing Edge
ATtiny48/88
Sample
Setup
SPI2X
R/W
0
0
SPSR
osc
127
is
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