ATTINY48-AUR Atmel, ATTINY48-AUR Datasheet - Page 133

• Manufacturer Part Number: ATTINY48-AUR
• Description: MCU AVR 4KB FLASH 12MHZ 32TQFP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY48-AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.5
8008G–AVR–04/11
Multi-master Bus Systems, Arbitration and Synchronization
Figure 15-6. Typical Data Transmission
The TWI protocol allows bus systems with several masters. Special concerns have been taken
in order to ensure that transmissions will proceed as normal, even if two or more masters initiate
a transmission at the same time. Two problems arise in multi-master systems:
Figure 15-7. SCL Synchronization Between Multiple Masters
SCL from
SCL from
SDA
SCL
Master A
Master B
SCL Bus
• An algorithm must be implemented allowing only one of the masters to complete the
• Different masters may use different SCL frequencies. A scheme must be devised to
transmission. All other masters should cease transmission when they discover that they have
lost the selection process. This selection process is called arbitration. When a contending
master discovers that it has lost the arbitration process, it should immediately switch to Slave
mode to check whether it is being addressed by the winning master. The fact that multiple
masters have started transmission at the same time should not be detectable to the slaves,
i.e. the data being transferred on the bus must not be corrupted.
synchronize the serial clocks from all masters, in order to let the transmission proceed in a
lockstep fashion. This will facilitate the arbitration process.
Line
START
Addr MSB
1
2
SLA+R/W
Addr LSB
7
TA
Counting Low Period
R/W
low
8
Masters Start
TB
ACK
9
low
Data MSB
1
2
Data Byte
TA
Counting High Period
high
7
Masters Start
TB
ATtiny48/88
Data LSB
high
8
ACK
9
STOP
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