M30625FGPGP#U7C Renesas Electronics America, M30625FGPGP#U7C Datasheet - Page 85
![IC M16C MCU FLASH 256K 128LQFP](/photos/12/29/122954/m30625fgpgp_u7c_sml.jpg)
M30625FGPGP#U7C
Manufacturer Part Number
M30625FGPGP#U7C
Description
IC M16C MCU FLASH 256K 128LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.QSK-62P_PLUS.pdf
(103 pages)
2.M30622SAFPU5.pdf
(308 pages)
3.M30620SPGPU3C.pdf
(423 pages)
Specifications of M30625FGPGP#U7C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
111
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 8.6
8.2.10
Chip Select Expansion Control Register
b7 b6 b5 b4
NOTES :
Software wait states can be inserted by using the PM17 bit in the PM1 register, the CS0W to CS3W bits in the
CSR register, and the CSE register. The SFR area is unaffected by these control bits. This area is always
accessed in 2 BCLK or 3 BCLK cycles as determined by the PM20 bit in the PM2 register. See Table 8.8 Bit
and Bus Cycle Related to Software Wait for details.
To use the RDY signal, set the corresponding CS3W to CS0W bit to “0” (with wait state). Figure 8.6 shows the
CSE Register. Table 8.8 shows the Bit and Bus Cycle Related to Software Wait. Figure 8.7 and 8.8 show the
Typical Bus Timings Using Software Wait.
1.
Set the CSiW bit (i = 0 to 3) in the CSR register to “0” (w ith w ait state) before w riting to the CSEi1W to CSEi0W bits.
If the CSiW bit needs to be set to “1” (w ithout w ait state), set the CSEi1W to CSEi0W bits to “00b” before setting it.
Jan 10, 2006
b3 b2 b1 b0
Software Wait
CSE Register
Bit Symbol
CSE00W
CSE01W
CSE10W
CSE11W
CSE20W
CSE21W
CSE30W
CSE31W
Page 68 of 390
Symbol
CSE
_____
CS0
_____
CS1
_____
CS2
_____
CS3
Wait Expansion Bit
Wait Expansion Bit
Wait Expansion Bit
Wait Expansion Bit
Bit Name
Address
001Bh
(1)
(1)
(1)
(1)
b1 b0
0 0 : 1 w ait
0 1 : 2 w aits
1 0 : 3 w aits
1 1 : Do not set
b3 b2
0 0 : 1 w ait
0 1 : 2 w aits
1 0 : 3 w aits
1 1 : Do not set
b5 b4
0 0 : 1 w ait
0 1 : 2 w aits
1 0 : 3 w aits
1 1 : Do not set
b7 b6
0 0 : 1 w ait
0 1 : 2 w aits
1 0 : 3 w aits
1 1 : Do not set
After Reset
Function
00h
RW
RW
RW
RW
RW
RW
RW
RW
RW
8. Bus
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