M30625FGPGP#U7C Renesas Electronics America, M30625FGPGP#U7C Datasheet - Page 105
![IC M16C MCU FLASH 256K 128LQFP](/photos/12/29/122954/m30625fgpgp_u7c_sml.jpg)
M30625FGPGP#U7C
Manufacturer Part Number
M30625FGPGP#U7C
Description
IC M16C MCU FLASH 256K 128LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.QSK-62P_PLUS.pdf
(103 pages)
2.M30622SAFPU5.pdf
(308 pages)
3.M30620SPGPU3C.pdf
(423 pages)
Specifications of M30625FGPGP#U7C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
111
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 10.6
PLL Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
NOTES :
1.
2.
3.
4.
0 0 1
Write to this register after setting the PRC0 bit in the PRCR register to “1” (w rite enable).
When the PM21 bit in the PM2 register is “1” (clock modification disable), w riting to this register has no effect.
These three bits can only be modified w hen the PLC07 bit = 0 (PLL turned off). The value once w ritten to this bit
cannot be modified.
Before setting this bit to “1”, set the CM07 bit in the CM0 register to “0” (main clock), set the CM17 to CM16 bits in the
CM1 register to “00b” (main clock undivided mode), and set the CM06 bit in the CM0 register to “0” (CM16 and CM17
bits enable).
Jan 10, 2006
PLC0 Register
Bit Symbol
(b6-b5)
Symbol
PLC00
PLC01
PLC02
PLC07
PLC0
(b3)
(b4)
(1, 2)
—
—
—
Page 88 of 390
PLL Multiplying Factor
Select Bit
Nothing is assigned. When w rite, set to “0”.
When read, its content is indeterminate.
Reserved Bit
Reserved Bit
Operation Enable Bit
(3)
Address
Bit Name
001Ch
(4)
b2 b1 b0
0 0 0 : Do not set
0 0 1 : Multiply by 2
0 1 0 : Multiply by 4
0 1 1 : Multiply by 6
1 0 0 : Multiply by 8
1 0 1 :
1 1 0 :
1 1 1 :
Set to “1”
Set to “0”
0: PLL Off
1: PLL On
Do not set
After Reset
0001X010b
Function
10. Clock Generation Circuit
RW
RW
RW
RW
RW
RW
RW
—
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