M30625FGPGP#U7C Renesas Electronics America, M30625FGPGP#U7C Datasheet - Page 167
M30625FGPGP#U7C
Manufacturer Part Number
M30625FGPGP#U7C
Description
IC M16C MCU FLASH 256K 128LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.QSK-62P_PLUS.pdf
(103 pages)
2.M30622SAFPU5.pdf
(308 pages)
3.M30620SPGPU3C.pdf
(423 pages)
Specifications of M30625FGPGP#U7C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
111
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 15.11
15.1.2.1
Timer A3
TA3OUT
(A phase)
TA3IN
(B phase)
Count source
NOTES :
ZP
This function initializes the timer count value to “0” by Z-phase (counter initialization) input during two-phase
pulse signal processing.
This function can only be used in Timer A3 event counter mode during two-phase pulse signal processing, free-
running type, x4 processing, with Z-phase entered from the ZP pin.
Counter initialization by Z-phase input is enabled by writing “0000h” to the TA3 register and setting the TAZIE
bit in the ONSF register to “1” (= Z-phase input enabled).
Counter initialization is accomplished by detecting Z-phase input edge. The active edge can be chosen to be the
rising or falling edge by using the POL bit in the INT2IC register. The Z-phase pulse width applied to the INT2
pin must be equal to or greater than one clock cycle of Timer A3 count source.
The counter is initialized at the next count timing after recognizing Z-phase input. Figure 15.11 shows the
Relationship Between the Two-Phase Pulse (A phase and B phase) and the Z-Phase.
If Timer A3 overflow or underflow coincides with the counter initialization by Z-phase input, a Timer A3
interrupt request is generated twice in succession. Do not use Timer A3 interrupt when using this function.
1. This timing diagram is for the case where the POL bit in the INT2IC register = 1 (= rising edge).
(1)
Jan 10, 2006
Counter Initialization by Two-Phase Pulse Signal Processing
Two-Phase Pulse (A phase and B phase) and the Z-Phase
Page 150 of 390
m
m+1
Input equal to or greater than one clock cycle
of count source
1
2
3
4
5
15. Timers
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