M30625FGPGP#U7C Renesas Electronics America, M30625FGPGP#U7C Datasheet - Page 248
![IC M16C MCU FLASH 256K 128LQFP](/photos/12/29/122954/m30625fgpgp_u7c_sml.jpg)
M30625FGPGP#U7C
Manufacturer Part Number
M30625FGPGP#U7C
Description
IC M16C MCU FLASH 256K 128LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.QSK-62P_PLUS.pdf
(103 pages)
2.M30622SAFPU5.pdf
(308 pages)
3.M30620SPGPU3C.pdf
(423 pages)
Specifications of M30625FGPGP#U7C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
111
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 17.41
Figure 17.42
17.2.1
17.2.2
NOTES :
1. This diagram applies to the case where the SiC register bits are set as follows:
2. When the SMi6 bit = 1 (internal clock), the SOUTi pin is placed in the high-impedance state after the transfer finishes.
3. If the SMi6 bit=0 (internal clock), the serial I/O starts sending or receiving data a maximum of 0.5 to 1.0 transfer clock cycles after writing to the
Signal written to the
SI/Oi internal clock
SMi2=0 (SOUTi output), SMi3=1 (SOUTi output, CLKi function), SMi4=0 (transmit data output at the falling edge and receive data input at
the rising edge of the transfer clock), SMi5=0 (LSB first) and SMi6=1 (internal clock)
SiTRR register.
Figure 17.41 shows the SI/Oi Operation Timing.
The SMi4 bit in the SiC register allows selection of the polarity of the transfer clock. Figure 17.42 shows the
Polarity of Transfer Clock.
i= 3, 4
SiTRR register
SOUTi output
SiIC register
Jan 10, 2006
CLKi output
SINi input
SI/Oi Operation Timing
CLK Polarity Selection
(1) When the SMi4 bit in the SiC register = 0
(2) When the SMi4 bit = 1
IR bit
SOUTi
SOUTi
CLKi
SINi
CLKi
SINi
Polarity of Transfer Clock
SI/Oi Operation Timing
NOTES:
i=3 and 4
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
"1"
"0"
1. This diagram applies to the case where the SiC register bits are set as follows:
2. When the SMi6 bit=1 (internal clock), a high level is output from the CLKi
3. When the SMi6 bit=1 (internal clock), a low level is output from the CLKi
SMi5=0 (LSB first) and SMi6=1 (internal clock)
pin if not transferring data.
pin if not transferring data.
0.5 to 1.0 cycle (max.)
Page 231 of 390
D0
D0
D0
D0
D1
D1
D1
D1
(3)
D0
D2
D2
D2
D2
D1
D3
D3
D3
D3
D2
D4
D4
D4
D4
D5
D5
D5
D5
D3
D6
D6
D6
D6
D4
D7
D7
D7
D7
D5
(NOTE 3)
(NOTE 2)
D6
17. Serial Interface
D7
(NOTE 2)
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