M30625FGPGP#U7C Renesas Electronics America, M30625FGPGP#U7C Datasheet - Page 217
![IC M16C MCU FLASH 256K 128LQFP](/photos/12/29/122954/m30625fgpgp_u7c_sml.jpg)
M30625FGPGP#U7C
Manufacturer Part Number
M30625FGPGP#U7C
Description
IC M16C MCU FLASH 256K 128LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.QSK-62P_PLUS.pdf
(103 pages)
2.M30622SAFPU5.pdf
(308 pages)
3.M30620SPGPU3C.pdf
(423 pages)
Specifications of M30625FGPGP#U7C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
111
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Manufacturer
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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 17.19
(1) 8-bit Data Transmit Timing (with a parity and 1 stop bit)
(1) 9-bit Data Transmit Timing (with no parity and 2 stop bits)
Transfer Clock
TE bit in UiC1
register
TI bit in UiC1
register
TXDi
TXEPT bit in
UiC0 register
IR bit in
SiTIC register
Transfer Clock
TE bit in UiC1
register
TI bit in UiC1
register
CTSi
TXDi
TXEPT bit in UiC0
register
IR bit in
SiTIC register
The above timing diagram applies to the case where the register bits are set
as follows:
The above timing diagram applies to the case where the register bits are set
as follows:
· PRYE bit in UiMR register = 1 (parity enabled)
· STPS bit in UiMR register = 0 (1 stop bit)
· CRD bit in UiC0 register = 0 (CTS/RTS enabled) and
· UiIRS bit = 1 (an interrupt request occurs when transmit completed):
· PRYE bit in UiMR register = 0 (parity disabled)
· STPS bit in UiMR register = 1 (2 stop bits)
· CRD bit in UiC0 register = 1 (CTS/RTS disabled)
· UiIRS bit = 0 (an interrupt request occurs when transmit
CRS bit = 0 (CTS selected)
buffer becomes empty):
i=0 to 2
i=0 to 2
Jan 10, 2006
U0IRS bit is bit 0 in UCON register
U1IRS bit is bit 1 in UCON register
U2IRS bit is bit 4 in U2C1 register
U0IRS bit is bit 0 in UCON register
U1IRS bit is bit 1 in UCON register
U2IRS bit is bit 4 in U2C1 register
Transmit Operation
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“H”
“L”
“1”
“0”
“1”
“0”
Start bit
Data is set in the UiTB register
ST
Page 200 of 390
Start bit
D0
ST
Set to “0” by an interrupt request acknowledgement or by program
D1
D0
Data is set in the UiTB register
D2
D1
Tc
D3
D2
Tc
D4
D3
Data is transferred from the UiTB register to the UARTi transmit register
D5
D4
D6
D5
The transfer clock stops momentarily, because an “H” single is applied to the CTS pin,
when the stop bit is verified.
The transfer clock resumes running as soon as an “L” single is applied to the CTS pin.
D7
D6
Stop
D8
D7
bit
Data is transferred from the UiTB register to
the UARTi transmit register
Parity
Set to “0” by an interrupt request acknowledgement or by program
bit
SP
P
SP
SP
Stop
Stop
bit
bit
ST
ST
TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT
TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT
D0
D0
fj : frequency of UiBRG count source
fEXT : frequency of UiBRG count source (external clock)
n : value set to UiBRG
fj : frequency of UiBRG count source
fEXT : frequency of UiBRG count source (external clock)
n : value set to UiBRG
(f1SIO, f2SIO, f8SIO, f32SIO)
D1
D1
(f1SIO, f2SIO, f8SIO, f32SIO)
D2
D2
D3
D3
D4
D4
Pulse stops because the TE bit is set to “0”
D5
D5
D6
D6
D7
D7
D8
P
SP
SP SP
17. Serial Interface
ST
ST
D0
D0
D1
D1
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