M30625FGPGP#U7C Renesas Electronics America, M30625FGPGP#U7C Datasheet - Page 198
![IC M16C MCU FLASH 256K 128LQFP](/photos/12/29/122954/m30625fgpgp_u7c_sml.jpg)
M30625FGPGP#U7C
Manufacturer Part Number
M30625FGPGP#U7C
Description
IC M16C MCU FLASH 256K 128LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.QSK-62P_PLUS.pdf
(103 pages)
2.M30622SAFPU5.pdf
(308 pages)
3.M30620SPGPU3C.pdf
(423 pages)
Specifications of M30625FGPGP#U7C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
111
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 17.5
UARTi Transmit Buffer Register (i=0 to 2)
UARTi Receive Buffer Register (i=0 to 2)
(b15)
(b15)
NOTES :
b7
b7
NOTES :
1. Use MOV instruction to w rite to this register.
1.
2.
3.
When the SMD2 to SMD0 bits in the UiMR register = 000b (serial interface disabled) or the RE bit in the UiC1 register =
0 (reception disabled), all of the SUM, PER, FER and OER bits are set to “0” (no error). The SUM bit is set to “0” (no
error) w hen all of the PER, FER and OER bits = 0 (no error).
Also, the PER and FER bits are set to “0” by reading the low er byte of the UiRB register.
The ABT bit is set to “0” by w riting “0” in a program. (Writing “1” has no effect.)
These error flags are disabled w hen the SMD2 to SMD0 bits are set to “001b” (clock synchronous serial
I/O mode) or to “010b” (I
Jan 10, 2006
UiTB and UiRB Registers
(b8)
(b8)
b0
b0
b7
b7
Transmit data
Nothing is assigned. When w rite, set to “0”.
When read, their contents are indeterminate.
Page 181 of 390
(b10-b9)
(b7-b0)
Symbol
SUM
(b8)
ABT
OER
FER
PER
2
Bit
—
—
—
C mode). When read, the contents are indeterminate.
b0
b0
—
—
Nothing is assigned. When w rite, set to “0”.
When read, their contents are “0”.
Arbitration Lost Detecting
Flag
Overrun Error Flag
Framing Error Flag
Parity Error Flag
Error Sum Flag
Symbol
U0TB
U1TB
U2TB
(2)
(1)
Bit Name
Symbol
U0RB
U1RB
U2RB
(1, 3)
(1,3)
(1, 3)
(1)
Function
03ABh to 03AAh
03A3h to 03A2h
037Bh to 037Ah
Receive data (D7 to D0)
Receive data (D8)
0 : Not detected
1 : Detected
0 : No overrun error
1 : Overrun error found
0 : No framing error
1 : Framing error found
0 : No parity error
1 : Parity error found
0 : No error
1 : Error found
Address
03A7h to 03A6h
03AFh to 03AEh
037Fh to 037Eh
Address
Function
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
After Reset
After Reset
17. Serial Interface
WO
RW
RW
RW
RO
RO
RO
RO
RO
RO
—
—
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