MC56F8013VFAE Freescale Semiconductor, MC56F8013VFAE Datasheet - Page 81

• Manufacturer Part Number: MC56F8013VFAE
• Description: IC DIGITAL SIGNAL CTLR 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8013VFAE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 2K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-LQFP
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: MC56F80xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 32 MIPs
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 26
• Data Ram Size: 4 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Rom Size: 16 KB
• Development Tools By Supplier: MC56F8037EVM, DEMO56F8014-EE, DEMO56F8013-EE
• Interface Type: SCI, SPI, I2C
• Minimum Operating Temperature: - 40 C
• For Use With: CPA56F8013 - BOARD SOCKET FOR MC56F8013APMOTOR56F8000E - KIT DEMO MOTOR CTRL SYSTEMDEMO56F8013-EE - BOARD DEMO FOR 56F8013
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

All peripherals, except the COP/watchdog timer, run at the system clock (peripheral bus) frequency
which is the same as the main processor frequency in this architecture. The COP timer runs at
MSTR_OSC / 1024. The maximum frequency of operation is SYS_CLK = 32MHz. The only exception is
the Quad Timer and PWM, which can be configured to operate at three times the system bus rate using
TCR and PCR controls, provided the PLL is active and selected.
6.6 Resets
The SIM supports four sources of reset, as shown in
external reset pin and the Power-On Reset (POR). The two synchronous sources are the software reset,
which is generated within the SIM itself by writing the SIM_CTRL register in
reset. The SIM uses these to generate resets for the internal logic. These are outlined in
first column lists the four primary resets which are calculated. The JTAG circuitry is reset by the Power-On
Reset. Columns two through five indicate which reset sources trigger these reset signals. The last column
provides additional detail.
Figure 6-15
use the Relaxation Oscillator Clock as their time base since other system clocks are inactive during this
phase of reset.
Freescale Semiconductor
1. The Quad Timer and PWM modules can be operated at three times the IPBus clock frequency.
EXTENDED_POR
CLKGEN_RST
PERIP_RST
CORE_RST
Reset Signal
provides a graphic illustration of the details in
POR
X
X
X
X
Table 6-4 Primary System Resets
External
56F8013/56F8011 Data Sheet, Rev. 12
Reset Sources
X
X
X
Software
X
X
X
Figure
COP
X
X
X
Table
6-15. The two asynchronous sources are the
Stretched version of POR. Relevant 64
Relaxation Oscillator Clock cycles after
POR deasserts.
Released 32 Relaxation Oscillator Clock
cycles after all reset sources have
released.
Releases 32 Relaxation Oscillator Clock
cycles after the CLKGEN_RST is
released.
Releases 32 SYS_CLK periods after
PERIP_RST is released.
6-4. Note that the POR_Delay blocks
Comments
Section
6.3.1, and the COP
Table
6-4. The
Resets
81
1
,