MC56F8013VFAE Freescale Semiconductor, MC56F8013VFAE Datasheet - Page 79

• Manufacturer Part Number: MC56F8013VFAE
• Description: IC DIGITAL SIGNAL CTLR 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8013VFAE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 2K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-LQFP
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: MC56F80xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 32 MIPs
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 26
• Data Ram Size: 4 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Rom Size: 16 KB
• Development Tools By Supplier: MC56F8037EVM, DEMO56F8014-EE, DEMO56F8013-EE
• Interface Type: SCI, SPI, I2C
• Minimum Operating Temperature: - 40 C
• For Use With: CPA56F8013 - BOARD SOCKET FOR MC56F8013APMOTOR56F8000E - KIT DEMO MOTOR CTRL SYSTEMDEMO56F8013-EE - BOARD DEMO FOR 56F8013
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.3.10.3
This field represents the lower 16 address bits of the “hard coded” I/O short address.
6.4 Clock Generation Overview
The SIM uses master clocks, 2X system clock at a maximum of 64MHz, from the OCCS module to
produce the peripheral and system (core and memory) clocks at a maximum of 32MHz. It divides the
master clock by two and gates it with appropriate power mode and clock gating controls. The high speed
peripheral clock from OCCS operates at three times the system clock for PWM and Quad Timer module
at a maximum of 96MHz.
The OCCS configuration controls the operating frequency of the SIM’s master clocks. In the OCCS, either
an external clock or the relaxation oscillator can be selected as the master clock source (MSTR_OSC). The
relaxation oscillator can be operated at full speed (8MHz), standby speed (200kHz), or powered down. An
8MHz clock can be multiplied to 192 MHz using the PLL and postscaled to provide a variety of high speed
clock rates. Either the postscaled PLL output or input clock of PLL signal can be selected to produce the
master clocks to the SIM. When the PLL is not selected, the high speed peripheral clock is disabled and
the 2X system clock is input clock from either internal relaxation oscillator or external clock source.
In combination with the OCCS module, the SIM provides power modes (see
(SIM_PCE register, CLK_DIS, ONCE_EBL), and clock rate controls (TCR, PCR) to provide flexible
control of clocking and power utilization. The SIM’s clock enable controls can be used to disable
individual clocks when not needed. The clock rate controls enable the high speed clocking option for the
Timer channels and PWM but require the PLL to be on and selected. Refer to the 56F801X Peripheral
User Manual for further details.
6.5 Power-Down Modes
The 56F8013/56F8011 operates in one of five Power-Down modes, as shown in
Freescale Semiconductor
Run
Base + $E
RESET
Write
Read
Mode
Figure 6-14 I/O Short Address Location Low Register (SIM_IOSALO)
Input/Output Short Address Location (ISAL[21:6])—Bits 15–0
15
1
Core and memory
clocks disabled
14
Table 6-3 Clock Operation in Power-Down Modes
1
Core Clocks
13
1
12
1
56F8013/56F8011 Data Sheet, Rev. 12
11
1
Peripheral clocks
enabled
Peripheral Clocks
10
1
9
1
8
1
ISAL[21:6]
Device is fully functional
7
1
6
1
5
1
Description
4
1
Section
Table 6-3
3
1
Clock Generation Overview
6.5), clock enables
2
1
.
1
1
0
1
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