MC56F8013VFAE Freescale Semiconductor, MC56F8013VFAE Datasheet - Page 78

• Manufacturer Part Number: MC56F8013VFAE
• Description: IC DIGITAL SIGNAL CTLR 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8013VFAE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 2K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-LQFP
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: MC56F80xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 32 MIPs
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 26
• Data Ram Size: 4 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Rom Size: 16 KB
• Development Tools By Supplier: MC56F8037EVM, DEMO56F8014-EE, DEMO56F8013-EE
• Interface Type: SCI, SPI, I2C
• Minimum Operating Temperature: - 40 C
• For Use With: CPA56F8013 - BOARD SOCKET FOR MC56F8013APMOTOR56F8000E - KIT DEMO MOTOR CTRL SYSTEMDEMO56F8013-EE - BOARD DEMO FOR 56F8013
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

With this register set, an interrupt driver can set the SIM_IOSALO register pair to point to its peripheral
registers and then use the I/O Short addressing mode to reference them. The ISR should restore this register
to its previous contents prior to returning from interrupt.
Note:
Note:
6.3.10.1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.3.10.2
This field represents the upper two address bits of the “hard coded” I/O short address.
78
Base + $D
RESET
Write
Read
The default value of this register set points to the EOnCE registers.
The pipeline delay between setting this register set and using short I/O addressing with the new value
is five instruction cycles.
Figure 6-13 I/O Short Address Location High Register (SIM_IOSAHI)
Reserved—Bits 15—2
Input/Output Short Address Location (ISAL[23:22])—Bits 1–0
2 bits from SIM_IOSAHI Register
15
Full 24-Bit for Short I/O Address
0
0
16 Bits from SIM_IOSALO Register
14
0
0
Figure 6-12 I/O Short Address Determination
13
0
0
6 Bits from I/O Short Address Mode Instruction
12
0
0
56F8013/56F8011 Data Sheet, Rev. 12
11
0
0
10
0
0
“
Hard Coded” Address Portion
9
0
0
8
0
0
7
0
0
6
0
0
5
0
0
Instruction Portion
4
0
0
3
0
0
Freescale Semiconductor
2
0
0
ISAL[23:22]
1
1
0
1