MC56F8002VWL Freescale Semiconductor, MC56F8002VWL Datasheet - Page 62

• Manufacturer Part Number: MC56F8002VWL
• Description: DSC 12K FLASH 32MHZ 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8002VWL

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 12KB (6K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 16
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 15x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-SOIC
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: MC56F80xx
• Core: 56800E
• Instruction Set Architecture: Dual Harvard
• Device Million Instructions Per Second: 32 MIPs
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 40
• Data Ram Size: 2 KB
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MC56F8006DEMO, APMOTOR56F8000E
• Interface Type: LIN, I2C, SCI, SPI
• Minimum Operating Temperature: - 40 C
• For Use With: APMOTOR56F8000E - KIT DEMO MOTOR CTRL SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Specifications
8.14
8.15
62
Oscillator current consumption in partial power down mode
Digital logic inputs amplitude (_2p5 signal)
DC analog input level (@ V
Max differential input voltage (@ Gain and V
Linearity (@ voltage gain)
1x
2x
4x
8x
16x
32x
Gain error (@ voltage gain)
1x
2x
4x
8x
16x
32x
Sampling frequency (pga_clk_2p5)
Input signal bandwidth
Internal voltage doubler clock frequency(pga_clk_doubler_2p5)
Operating temperature
COP Specifications
PGA Specifications
Oscillator output frequency
Parameter
low power mode (pga_lp_2p5 negated)
Parameter
normal mode (pga_lp_2p5 asserted)
DD
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3
= avdd3p3)
PGA S/H stage disabled (BP=1)
PGA S/H stage enabled (BP=0)
General Purpose mode (BP=1)
Motor Control mode (BP=0)
Table 33. COP Specifications
Table 34. PGA Specifications
DD
= avdd3p3)
Symbol
LPFosc
IDD
V
Symbol
BW
DIFFMAX
SF
VD
V
V
A
L
2p5
T
max
IL
V
V
max
clk
Min
500
1 – 1/2 LSB
2 – 1/2 LSB
16 – 4 LSB
32 – 4 LSB
4 – 1 LSB
8 – 1 LSB
Min
100
–40
0
1000
TBD
Typ
PGA sampling rate/2
PGA sampling rate/8
(V
DD
1 + 1/2 LSB
2 + 1/2 LSB
16 + 4 LSB
32 + 4 LSB
4 + 1 LSB
8 + 1 LSB
V
– 1) x 0.5/gain
DD
Freescale Semiconductor
2000
Max
2.75
V
125
1%
1500
DD
8
4
Max
– 0.5
Unit
MHz
Unit
Hz
nA
V/V
V/V
kHz
Hz
o
V
V
V
C