MC56F8002VWL Freescale Semiconductor, MC56F8002VWL Datasheet - Page 53

• Manufacturer Part Number: MC56F8002VWL
• Description: DSC 12K FLASH 32MHZ 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8002VWL

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 12KB (6K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 16
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 15x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-SOIC
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: MC56F80xx
• Core: 56800E
• Instruction Set Architecture: Dual Harvard
• Device Million Instructions Per Second: 32 MIPs
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 40
• Data Ram Size: 2 KB
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MC56F8006DEMO, APMOTOR56F8000E
• Interface Type: LIN, I2C, SCI, SPI
• Minimum Operating Temperature: - 40 C
• For Use With: APMOTOR56F8000E - KIT DEMO MOTOR CTRL SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

8.11
8.12
Reference
Freescale Semiconductor
1
2
Delay from Interrupt Assertion to Fetch of first
In the formulas, T = system clock cycle and T
At 4 MHz (used coming out of reset and stop modes), T = 250 ns.
Parameters listed are guaranteed by design.
RESET deassertion to First Address Fetch
Minimum GPIO pin Assertion for Interrupt
Minimum RESET Assertion Duration
GPIO pin
Figure
(Input)
Reset, Stop, Wait, Mode Select, and Interrupt Timing
External Oscillator (XOSC) Characteristics
instruction (exiting Stop)
Characteristic
9, and
Figure
Table 26. Reset, Stop, Wait, Mode Select, and Interrupt Timing
Figure 22. GPIO Interrupt Timing (Negative Edge-Sensitive)
10, and
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3
All address and data buses described here are internal.
Figure 11
osc
for crystal or resonator circuits.
= oscillator clock cycle. For an operating frequency of 32 MHz, T = 31.25 ns.
Symbol
t
t
t
RDA
t
RA
IW
IF
t
IW
NOTE
96T
Typical Min
OSC
4T
2T
—
+ 64T
97T
Typical Max
OSC
6T
—
—
+ 65T
1,2
Unit
ns
ns
ns
ns
Specifications
See Figure
Figure 22
—
—
—
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