MC56F8002VWL Freescale Semiconductor, MC56F8002VWL Datasheet - Page 55

• Manufacturer Part Number: MC56F8002VWL
• Description: DSC 12K FLASH 32MHZ 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8002VWL

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 12KB (6K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 16
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 15x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-SOIC
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: MC56F80xx
• Core: 56800E
• Instruction Set Architecture: Dual Harvard
• Device Million Instructions Per Second: 32 MIPs
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 40
• Data Ram Size: 2 KB
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MC56F8006DEMO, APMOTOR56F8000E
• Interface Type: LIN, I2C, SCI, SPI
• Minimum Operating Temperature: - 40 C
• For Use With: APMOTOR56F8000E - KIT DEMO MOTOR CTRL SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

8.13.1
Freescale Semiconductor
•
•
•
Access time (time to data active from high-impedance
Disable time (hold time to high-impedance state)
Tri-stated, when a bus or signal is placed in a high impedance state
Data Valid state, when a signal level has reached V
Data Invalid state, when a signal level is in transition between V
Data set-up time required for inputs
Serial Peripheral Interface (SPI) Timing
Data hold time required for inputs
Data Invalid State
Clock (SCK) high time
Clock (SCK) low time
Data1 Valid
Enable lead time
Data1
Enable lag time
Characteristic
Cycle time
Master
Master
Master
Master
Master
Master
Master
Slave
Slave
Slave
Slave
Slave
Slave
Slave
state)
Slave
Slave
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3
Data Active
Data2 Valid
Figure 24. Signal States
Table 28. SPI Timing
Data2
Symbol
OL
t
t
t
t
t
ELD
ELG
t
t
CH
DS
DH
t
t
CL
or V
C
D
A
OH
Data
Three-stated
OL
62.5
Min
125
125
4.8
3.7
31
50
31
50
31
20
1
—
—
0
0
2
and V
OH
Max
15.2
15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Data3 Valid
Data Active
Data3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
See Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure 28
Figure
Figure 28
Figure
Figure 28
Figure
Figure 28
Figure 28
Figure 28
Figure 28
Figure 28
Figure 28
Specifications
26,
27,
26,
27,
26,
27,
26,
27,
25,
25,
25,
25,
55