MC56F8002VWL Freescale Semiconductor, MC56F8002VWL Datasheet - Page 58

• Manufacturer Part Number: MC56F8002VWL
• Description: DSC 12K FLASH 32MHZ 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8002VWL

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 12KB (6K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 16
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 15x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-SOIC
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: MC56F80xx
• Core: 56800E
• Instruction Set Architecture: Dual Harvard
• Device Million Instructions Per Second: 32 MIPs
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 40
• Data Ram Size: 2 KB
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MC56F8006DEMO, APMOTOR56F8000E
• Interface Type: LIN, I2C, SCI, SPI
• Minimum Operating Temperature: - 40 C
• For Use With: APMOTOR56F8000E - KIT DEMO MOTOR CTRL SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Specifications
8.13.2
58
1
2
Deviation of slave node clock relative to
Parameters listed are guaranteed by design.
f
(max. 96 MHz) for the 56F8006/56F8002 device.
MAX
Deviation of slave node clock from
Minimum break character length
SCLK (CPOL = 0)
SCLK (CPOL = 1)
the master node clock after
is the frequency of operation of the SCI in MHz, which can be selected system clock (max. 32 MHz) or 3x system clock
nominal clock rate before
RXD pulse width
TXD pulse width
synchronization
synchronization
Characteristic
Serial Communication Interface (SCI) Timing
(Output)
Baud rate
(Input)
(Input)
(Input)
(Input)
MISO
MOSI
SS
2
t
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3
DV
t
DS
t
Figure 28. SPI Slave Timing (CPHA = 1)
A
F
t
TOL_UNSYNCH
F
ELD
TOL_SYNCH
Symbol
RXD
Slave MSB out
TXD
T
BREAK
MSB in
BR
Table 29. SCI Timing
PW
PW
t
C
LIN Slave Mode
t
t
CH
CL
0.965/BR
0.965/BR
t
DH
Min
–14
t
t
–2
13
11
—
CH
CL
Bits 14–1
t
Bits 14–1
DV
1
t
F
t
R
(f
1.04/BR
1.04/BR
MAX
Max
14
—
—
2
/16)
t
F
t
R
t
DI
Master node
LSB in
Slave node
bit periods
bit periods
Slave LSB out
Mbps
Unit
ns
ns
%
%
Freescale Semiconductor
t
ELG
t
D
See Figure
Figure 29
Figure 30
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