Z8F1233QH020SG Zilog, Z8F1233QH020SG Datasheet - Page 97

• Manufacturer Part Number: Z8F1233QH020SG
• Description: IC ENCORE XP MCU FLSH 12K 20QFN
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F1233QH020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Other names: 269-4656

®
Z8 Encore!
F0830 Series
Product Specification
87
WDT Interrupt in STOP Mode
®
If configured to generate an interrupt when a time-out occurs and the Z8 Encore!
F0830
Series devices are in STOP mode, the Watchdog Timer automatically initiates a Stop
Mode Recovery and generates an interrupt request. Both the WDT status bit and the STOP
bit in the Watchdog Timer control register are set to 1 following a WDT time-out in STOP
mode. See
Reset and Stop Mode Recovery
on page 23 for more information about Stop
Mode Recovery.
If interrupts are enabled, following completion of the Stop Mode Recovery, the eZ8 CPU
responds to the interrupt request by fetching the Watchdog Timer interrupt vector and
executes the code from the vector address.
WDT Reset in Normal Operation
If configured to generate a reset when a time-out occurs, the Watchdog Timer forces the
device into the System Reset state. The WDT status bit in the Watchdog Timer control
register is set to 1. See
Reset and Stop Mode Recovery
on page 23 for more information
about system reset.
WDT Reset in STOP Mode
If configured to generate a reset when a time-out occurs and the device is in STOP mode,
the Watchdog Timer initiates a Stop Mode Recovery. Both the WDT status bit and the
STOP bit in the Watchdog Timer control register are set to 1 following WDT time-out in
STOP mode. See
Reset and Stop Mode Recovery
on page 23 for more information.
Watchdog Timer Reload Unlock Sequence
Writing the unlock sequence to the Watchdog Timer (WDTCTL) control register address,
unlocks the three Watchdog Timer reload byte registers (WDTU, WDTH, and WDTL) to
allow changes to the time-out period. These Write operations to the WDTCTL register
address produce no effect on the bits in the WDTCTL register. The locking mechanism
prevents spurious writes to the reload registers. The following sequence is required to
unlock the Watchdog Timer reload byte registers (WDTU, WDTH, and WDTL) for write
access:
1. Write 55
to the Watchdog Timer control register (WDTCTL).
H
2. Write AA
to the Watchdog Timer control register (WDTCTL).
H
3. Write the Watchdog Timer reload upper byte register (WDTU).
4. Write the Watchdog Timer reload high byte register (WDTH).
5. Write the Watchdog Timer reload low byte register (WDTL).
All three Watchdog Timer reload registers must be written in the order listed above. There
must be no other register writes between each of these operations. If a register write
PS025111-1207
Watchdog Timer