Z8F1233QH020SG Zilog, Z8F1233QH020SG Datasheet - Page 139

• Manufacturer Part Number: Z8F1233QH020SG
• Description: IC ENCORE XP MCU FLSH 12K 20QFN
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F1233QH020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Other names: 269-4656

PS025111-1207
Table 88. Read Status Byte
BITS
FIELD
DEFAULT
VALUE
Power Failure Protection
status byte resides in working register R1. The bit fields of this status byte are defined in
Table
The read routine uses 16 bytes of stack space in addition to the one byte of address pushed
by the user code. Sufficient memory must be available for this stack usage.
Because of the Flash memory architecture, NVDS reads exhibit a non-uniform execution
time. A read operation takes between 71 µs and 258 µs (assuming a 20 MHz system
clock). Slower system clock speeds result in proportionally higher execution times.
NVDS byte reads from invalid addresses (those exceeding the NVDS array size) return
0xff
The status byte returned by the NVDS read routine is zero for successful read. If the status
byte is non-zero, there is a corrupted value in the NVDS array at the location being read.
In this case, the value returned in R0 is the byte most recently written to the array that does
not have an error.
The NVDS routines employ error checking mechanisms to ensure a power failure
endangers only for the most recently written byte. Bytes previously written to the array are
not perturbed. For this protection to function, the VBO must be enabled (See
Modes
Bit Address Space
7
0
Reserved—Must be 0.
DE—Data Error
When reading a NVDS address, if an error is found in the latest data corresponding to
this NVDS address, this bit is set to 1. NVDS source code steps forward until finding
a valid data at this address.
FE—Flash Error
If Flash error is detected, this bit is set to 1.
IGADDR—Illegal address
When NVDS byte reads from invalid addresses (those exceeding the NVDS array
size) occur, this bit is set to 1.
. Illegal read operations have a 6 µs execution time.
88. Also, the user code should pop the address byte off the stack.
on page 33) and configured for a threshold voltage of 2.4 V or greater (See
Reserved
6
0
on page 122).
5
0
DE
4
0
Reserved
3
0
FE
Z8 Encore!
2
0
Product Specification
Non-Volatile Data Storage
IGADDR Reserved
0
1
®
F0830 Series
Low-Power
0
Trim
0
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