Z8F1233QH020SG Zilog, Z8F1233QH020SG Datasheet - Page 34
Z8F1233QH020SG
Manufacturer Part Number
Z8F1233QH020SG
Description
IC ENCORE XP MCU FLSH 12K 20QFN
Manufacturer
Zilog
Series
Encore!®r
Specifications of Z8F1233QH020SG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, LED, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
For Use With
770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
Other names
269-4656
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8F1233QH020SG
Manufacturer:
Zilog
Quantity:
670
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Table 8. Reset and Stop Mode Recovery Characteristics and Latency (Continued)
Reset Sources
PS025111-1207
Reset Type
Stop Mode Recovery
Stop Mode Recovery with
crystal oscillator enabled
During a system RESET or Stop Mode Recovery, the Z8 Encore!
held in reset for about 66 cycles of the Internal Precision Oscillator. If the crystal oscillator
is enabled in the Flash option bits, the reset period is increased to about 5000 IPO cycles.
When a reset occurs because of a low voltage condition or Power-On Reset, the reset delay
is measured from the time that the supply voltage first exceeds the POR level (discussed
later in this chapter). If the external pin reset remains asserted at the end of the reset
period, the device remains in reset until the pin is deasserted.
At the beginning of reset, all GPIO pins are configured as inputs with pull-up resistor
disabled, except PD0 which is shared with the reset pin. On reset, the port D0 pin is
configured as a bidirectional open-drain reset. This pin is internally driven low during port
reset, after which the user code may reconfigure this pin as a general purpose output.
During reset, the eZ8 CPU and on-chip peripherals are idle; however, the on-chip crystal
oscillator and Watchdog Timer Oscillator continues to run.
On reset, control registers within the register file that have a defined reset value are loaded
with their reset values. Other control registers (including the Stack Pointer, Register
Pointer, and Flags) and general purpose RAM are undefined following the reset. The eZ8
CPU fetches the reset vector at program memory addresses
that value into the program counter. Program execution begins at the reset vector address.
Because the control registers are re-initialized by a system reset, the system clock after
reset is always the IPO. User software must reconfigure the oscillator control block, to
enable and select the correct system clock source.
Table 9
on page 25 lists the possible sources of a system reset.
Reset Characteristics and Latency
Control Registers
Unaffected, except
WDT_CTL and
OSC_CTL registers
Unaffected, except
WDT_CTL and
OSC_CTL registers
eZ8
CPU
Reset About 66 Internal Precision Oscillator
Reset About 5000 Internal Precision Oscillator
Reset Latency (Delay)
cycles
cycles
Z8 Encore!
0002H
Reset and Stop Mode Recovery
Product Specification
®
F0830 Series device is
and
0003H
®
F0830 Series
and loads
24
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