Z8F1233QH020SG Zilog, Z8F1233QH020SG Datasheet - Page 90

IC ENCORE XP MCU FLSH 12K 20QFN

Z8F1233QH020SG

Manufacturer Part Number
Z8F1233QH020SG
Description
IC ENCORE XP MCU FLSH 12K 20QFN
Manufacturer
Zilog
Series
Encore!®r
Datasheets

Specifications of Z8F1233QH020SG

Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, LED, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
For Use With
770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
Other names
269-4656

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
Z8F1233QH020SG
Manufacturer:
Zilog
Quantity:
670
Table 51. Timer 0–1 PWM High Byte Register (TxPWMH)
Table 52. Timer 0–1 PWM Low Byte Register (TxPWML)
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
PS025111-1207
Timer 0-1 PWM High and Low Byte Registers
Timer 0–1 Control Registers
R/W
R/W
0
0
7
7
maximum count value, which initiates a timer reload to
these two bytes form the 16-bit compare value.
The timer 0-1 PWM high and low byte (TxPWMH and TxPWML) registers
Table
the capture and CAPTURE/COMPARE modes.
PWMH and PWML—Pulse Width Modulator high and low bytes
These two bytes, {PWMH[7:0], PWML[7:0]}, form a 16-bit value that is compared to the
current 16-bit timer count. When a match occurs, the PWM output changes state. The
PWM output value is set by the TPOL bit in the timer control register (TxCTL1).
The TxPWMH and TxPWML registers also store the 16-bit captured timer value when
operating in capture or CAPTURE/COMPARE modes.
Time 0–1 Control Register 0
The timer control register 0 (TxCTL0) and timer control register 1 (TxCTL1) determine
the timer operating mode. It also includes a programmable PWM deadband delay, two bits
to configure timer interrupt definition, and a status bit to identify, if the most recent timer
interrupt is caused by an input Capture event.
52) controls the PWM operations. These registers also store the capture values for
R/W
R/W
6
0
6
0
R/W
R/W
5
0
5
0
R/W
R/W
0
0
4
4
F04H, F0CH
F05H, F0DH
PWMH
PWML
R/W
R/W
3
0
3
0
0001H
R/W
R/W
Z8 Encore!
0
0
2
2
. In COMPARE mode,
Product Specification
R/W
R/W
1
0
1
0
®
F0830 Series
(Table 51
R/W
R/W
0
0
0
0
Timers
and
80

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