Z8F1233QH020SG Zilog, Z8F1233QH020SG Datasheet - Page 38

• Manufacturer Part Number: Z8F1233QH020SG
• Description: IC ENCORE XP MCU FLSH 12K 20QFN
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F1233QH020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Other names: 269-4656

Stop Mode Recovery
PS025111-1207
External Reset Indicator
On-Chip Debugger Initiated Reset
reset pulse of three clock cycles in duration might trigger a reset and a reset pulse of four
cycles in duration always triggers a reset.
While the RESET input pin is asserted low, the Z8 Encore!
in the Reset state. If the RESET pin is held low beyond the system reset time-out, the
device exits the Reset state on the system clock rising edge following RESET pin
deassertion. Following a system reset initiated by the external RESET pin, the EXT status
bit in the reset status (RSTSTAT) register is set to 1.
During system reset or when enabled by the GPIO logic, the RESET pin functions as an
open-drain (active low) RESET mode indicator in addition to the input functionality. This
reset output feature allows an Z8 Encore! F0830 Series device to reset other components
to which it is connected, even if that reset is caused by internal sources such as POR, VBO
or WDT events. See
After an internal Reset event occurs, the internal circuitry begins driving the RESET pin
low. The RESET pin is held low by the internal circuitry until the appropriate delay listed
in
A Power-on reset can be initiated using the On-Chip Debugger by setting the
the OCD control register. The OCD block is not reset, but the rest of the chip goes through
a normal system reset. The
the system reset, the
The device enters the STOP mode when the STOP instruction is executed by the eZ8
CPU. See
Stop Mode Recovery, the CPU is held in reset for about 66 IPO cycles if the crystal
oscillator is disabled or about 5000 cycles if it is enabled.
Stop Mode Recovery does not affect the on-chip registers other than the reset status
(RSTSTAT) register and the oscillator control register (OSCCTL). After any Stop Mode
Recovery, the IPO is enabled and selected as the system clock. If another system clock
source is required or IPO disabling is required, the Stop Mode Recovery code must
reconfigure the oscillator control block such that the correct system clock source is
enabled and selected.
The eZ8 CPU fetches the reset vector at program memory addresses
and loads that value into the program counter. Program execution begins at the reset vector
address. Following Stop Mode Recovery, the STOP bit in the reset status (RSTSTAT)
Table 8
Low-Power Modes
has elapsed.
Port A–D Control Registers
POR
bit in the reset status (RSTSTAT) register is set.
RST
on page 33 for detailed STOP mode information. During
bit automatically clears during the system reset. Following
on page 44.
®
Z8 Encore!
F0830 Series devices remain
Reset and Stop Mode Recovery
Product Specification
0002H
®
F0830 Series
and
RST
0003H
bit in
28