Z8F1233QH020SG Zilog, Z8F1233QH020SG Datasheet - Page 87
Z8F1233QH020SG
Manufacturer Part Number
Z8F1233QH020SG
Description
IC ENCORE XP MCU FLSH 12K 20QFN
Manufacturer
Zilog
Series
Encore!®r
Specifications of Z8F1233QH020SG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, LED, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
For Use With
770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
Other names
269-4656
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8F1233QH020SG
Manufacturer:
Zilog
Quantity:
670
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PS025111-1207
Reading the Timer Count Values
registers. When the Capture event occurs, an interrupt is generated, the count value in the
timer high and low byte registers is reset to
INPCAP bit in TxCTL1 register is set to indicate that the timer interrupt is caused by an
input Capture event.
If no Capture event occurs, the timer counts up to the 16-bit compare value stored in the
timer reload high and low byte registers. On reaching the compare value, the timer
generates an interrupt, the count value in the timer high and low byte registers is reset to
0001H
that the timer interrupt is not caused by an input Capture event.
Follow the steps below for configuring a timer for CAPTURE/COMPARE mode and for
initiating the count:
1. Write to the timer control register to:
2. Write to the timer high and low byte registers to set the starting count value (typically
3. Write to the timer reload high and low byte registers to set the compare value.
4. Enable the timer interrupt and set the timer interrupt priority by writing to the relevant
5. Configure the associated GPIO port pin for the timer input alternate function.
6. Write to the timer control register to enable the timer.
7. Counting begins on the first appropriate transition of the timer input signal. No
In CAPTURE/COMPARE mode, the elapsed time from timer start to Capture event can be
calculated using the following equation:
The current count value in the timers can be read while counting (enabled). This capability
has no effect on Timer operation. When the timer is enabled and the timer high byte
–
–
–
–
0001H
interrupt registers.By default, the timer interrupt are generated for both input capture
and Reload events. You can configure the timer interrupt to be generated only at the
input Capture event or the Reload event by setting TICONFIG field of the TxCTL1
register.
interrupt is generated by the first edge.
and counting resumes. The INPCAP bit in TxCTL1 register is cleared to indicate
Capture Elapsed Time (s)
Disable the timer
Configure the timer for CAPTURE/COMPARE mode.
Set the prescale value.
Set the capture edge (rising or falling) for the timer input.
).
=
(
---------------------------------------------------------------------------------------------------------
Capture Value Start Value
System Clock Frequency (Hz)
0001H
–
and the counting resumes. The
)
Z8 Encore!
×
Prescale
Product Specification
®
F0830 Series
Timers
77
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