LPC1113FHN33/301,5 NXP Semiconductors, LPC1113FHN33/301,5 Datasheet - Page 57

• Manufacturer Part Number: LPC1113FHN33/301,5
• Description: IC MCU 32BIT 24KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC1100r

Specifications of LPC1113FHN33/301,5

• Program Memory Type: FLASH
• Program Memory Size: 24KB (24K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC11
• Core: ARM Cortex M0
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SPI, UART
• Number Of Programmable I/os: 28
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1100
• Device Core: ARM Cortex M0
• Device Core Size: 32b
• Frequency (max): 50MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 33
• Package Type: HVQFN EP
• Package: 33HVQFN EP
• Family Name: LPC1100
• Maximum Speed: 50 MHz
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4951; 935290776551

NXP Semiconductors
14. Revision history
Table 21.
LPC1111_12_13_14
Product data sheet
Document ID
LPC1111_12_13_14 v.2
Modifications:
LPC1111_12_13_14 v.1
Revision history
Release date
20100818
20100416
•
•
•
•
•
•
•
•
•
V
t
Deep-sleep mode functionality changed to allow BOD and watchdog oscillator as the
only analog blocks allowed to remain running in Deep-sleep mode
V
Reset state of pins and start logic functionality added in
Section 7.16.1
Section “Memory mapping control” removed.
V
Section 9.3
DS
ESD
DD
OH
updated for SPI in master mode
range changed to 3.0 ≤ V
and I
All information provided in this document is subject to legal disclaimers.
limit changed to −6500 V (min) /+6500 V (max) in
OH
added.
specifications updated for high-drive pins in
Rev. 2 — 18 August 2010
Data sheet status
Product data sheet
Product data sheet
added.
DD
≤ 3.6 V in
(Table
-
Change notice
-
32-bit ARM Cortex-M0 microcontroller
17).
Table
LPC1111/12/13/14
15.
Table
Table 3
Supersedes
LPC1111_12_13_14 v.1
-
Table
6.
7.
to
Table
© NXP B.V. 2010. All rights reserved.
(Section
5.
7.15.5.2).
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