M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 526
![IC M32C MCU FLASH 100LQFP](/photos/12/22/122251/m30853fjgp_u3_sml.jpg)
M30853FJGP#U3
Manufacturer Part Number
M30853FJGP#U3
Description
IC M32C MCU FLASH 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(364 pages)
2.M30853FHFPD5.pdf
(94 pages)
3.M30853FHFPU3.pdf
(544 pages)
Specifications of M30853FJGP#U3
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30853FJGP#U3M30853FJGP#D5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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0.41
Rev.
Mar., 04
REVISION HISTORY
Date
411 - 433 Overall Structural Revision
Page
2 - 3
364
369
373
376
383
385
390
392
409
410
28
46
47
50
51
52
54
58
63
82
83
84
• Figure 23.6 P0 toP15 Registers modified
• Figure 23.11 PSL0 Register and PSL1 Register Note 1 added to PSL1
• Figure 23.15 PUR0 Register, PUR1 Register and PUR2 Register “Address
• Figure 23.18 IPSA Register b0 bit changed to IPSA_0 bit
Flash Memory Version
• 24.2.1 ROM Code Protect Function modified
• 24.2.2 ID Code Check Function modified
• Table 24.3 EW0 Mode and EW1 Mode Note 1 modified
• Figure 24.6 How to Enter and Exit EW1 Note 3 modified
• 24.3.4.4 Interrupts (EW1 Mode) modified
• Figure 24.18 Circuit Application in Standard Serial I/O Mode revised
• 24.5.2 ROM Control Protect Function modified
Precautions
Overview
• Tables 1.1 and 1.2 M32C/85 Group Performance Shortest Instruction
SFR
• Value after RESET of G0RB register revised
Reset
• 5.1.2 Hardware Reset 2 revised
• Figure 5.2 Reset Sequence modified
• 5.5 Voltage Detect Circuit revised
• Figure 5.4 Reset Circuit Block Diagram modified
• Figure 5.5 WDC Register Note 2. revised
• Figure 5.6 VCR1 and VCR2 Registers Bit 5 changed to reserved bit; Notes 3
• Figure 5.8 Hardware Reset 2 modified
Processor Mode
• 6.2.2 Applying VSS to CNVSS Pin revised
Bus
• 7.1.3.2 Multiplexed Bus revised
Clock Generation Circuit
• Table 8.1 Clock Generation Circuit Specifications Reference added to PLL
• Figure 8.1 Clock Genration Circuit modified
• Figure 8.2 CM0 Register Note 6 revised
register
bus” changed to “bus control pins”
Execution Time and Power Consumption modified
and 4 deleted
Frequency Synthesizer
M32C/85 Group(M32C/85, M32C/85T) Hardware Manual
C-7
Description
Summary
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