M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 359
![IC M32C MCU FLASH 100LQFP](/photos/12/22/122251/m30853fjgp_u3_sml.jpg)
M30853FJGP#U3
Manufacturer Part Number
M30853FJGP#U3
Description
IC M32C MCU FLASH 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(364 pages)
2.M30853FHFPD5.pdf
(94 pages)
3.M30853FHFPU3.pdf
(544 pages)
Specifications of M30853FJGP#U3
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30853FJGP#U3M30853FJGP#D5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M
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3
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2
Figure 23.10 C0TSR and C1TSR Registers
0
C
23.1.8 CANi Time Stamp Register (CiTSR Register)
1
9
8 /
0 .
B
0
3
5
0
G
3
The CiTSR register is a 16-bit counter. The TSPRE1 and TSPRE0 bits in the CiCTLR0 register select
the CAN bus bit clock divided by 1, 2, 3 or 4 as the count source for the CiTSR register.
When data transmission or reception is completed, the value of the CiTSR register is automatically
stored into the message slot.
In loopback mode, when either data frame receive message slot or remote frame receive message
slot is available to store the message, the value of the CiTSR register is also stored into the message
slot when data reception is completed. The value of the CiTSR register is not stored when data
transmission is completed.
The CiTSR register starts a counter increment when the RESET1 and RESET0 bits in the CiCTLR0
register are set to "0".
The CiTSR register is set to "0000
J
CANi Time Stamp Register
b15
7
u
o r
0 -
. l
• at the next count timing after the CiTSR register is set to "FFFF
• when the RESET1 and RESET0 bits are set to "1" (CAN module reset) by program; or
• when the TSRESET bit is set to "1" (CiTSR register reset) by program.
CAN bus bit clock =
u
NOTES:
0
1
p
, 1
0
3
1. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after
(
2
M
reset and supplying the clock to the CAN module.
0
3
0
b8
2
5
C
b7
8 /
Page 334
, 5
M
3
2
b0
C
f o
8 /
Value of time stamp
4
5
CAN bit time
9
) T
Symbol
C0TSR
C1TSR
4
1
16
(i=0, 1)
":
Address
0209
0289
16 -
16 -
0208
0288
Function
16
16
(i=0, 1)
After Reset
0000
0000
16
16
16
";
(1)
RW
RO
23. CAN Module
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