M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 521
M30853FJGP#U3
Manufacturer Part Number
M30853FJGP#U3
Description
IC M32C MCU FLASH 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(364 pages)
2.M30853FHFPD5.pdf
(94 pages)
3.M30853FHFPU3.pdf
(544 pages)
Specifications of M30853FJGP#U3
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30853FJGP#U3M30853FJGP#D5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Rev.
REVISION HISTORY
Date
76, 77
Page
53
55
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88
• Figure 5.7 D4INT Register Bit name and function of the D41 bit modified; b7 to
• 5.5.1 Voltage Down Detection Interrupt New information added
• Table 5.2 Conditions to Generate the Voltage Down Detect Interrupt Request
• Figure 5.9 Voltage Down Detect Interrupt Generation Circuit revised
• Figure 5.10 Voltage Down Detect Interrupt Generation Circuit Operation
• 5.6 Limitations on Exiting Stop/Wait Mode modified
Processor Mode
PM2 register moved to Clock Generation Circuit
• Figure 6.2 PM1 Register Value after RESET modified; b6 bit changed to re-
• Figure 6.3 Memory Map in Each Processor Mode Block A changed to re-
Bus
• 7.1.3.1 Separate Bus modified
Table 7.2 Processor Mode and Functions Original Note 4 deleted and Note 5
• 7.2.4 Bus Timing modified
• Figure 7.3 EWCR0 to EWCR3 Register Notes 1 to 3 added
• 7.2.4.1 Bus Cycle with Recovery Cycle Added modified
• 7.2.5 Page Mode Control Function modified
• Figure 7.10 PWCR0 Register, Figure 7.11 PWCR1 Register Note 2 added
• Figure 7.12 External Bus with the page Mode Control Function modified
• Figure 7.14 RD Signal Output Extended by RDY Signal revised
Clock Generation Circuit
Chapter title modified from “System Clock”
• Table 8.1 Clock Generation Circuit Specifications revised
• Figure 8.1 Clock Generation Circuit revised
• Figure 8.2 CM0 Register b3 bit changed from Reserved Bit to the CM03 bit; Bit
• Figure 8.3 CM1 Register Bit name of the CM 17 bit modified
• Figure 8.4 MCD Register Value after RESET modified; b5 to b7 bits changed to
• Figure 8.5 CM2 Register Bit name and function of the CM21 bit modified; Bit
• Figure 8.6 TCSPR and CPSRF Registers b4 to b6 bits in the TCSPR register
b6 changed to RO reserved bits; Note 2 modified
Table revised; Note 2 modified; Note 3 added
Example revised
served bit
served space
moved up to become new Note 4
name and function of the CM07 bit modified; Note 11 added
RO reserved bits
name of the CM23 bit modified; Note 6 modified; Note 7 deleted
changed to RO reserved bits
M32C/85 Group(M32C/85, M32C/85T) Hardware Manual
_____
C-2
Description
Summary
_______
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