M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 201
![IC M32C MCU FLASH 100LQFP](/photos/12/22/122251/m30853fjgp_u3_sml.jpg)
M30853FJGP#U3
Manufacturer Part Number
M30853FJGP#U3
Description
IC M32C MCU FLASH 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(364 pages)
2.M30853FHFPD5.pdf
(94 pages)
3.M30853FHFPU3.pdf
(544 pages)
Specifications of M30853FJGP#U3
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30853FJGP#U3M30853FJGP#D5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R
R
M
e
E
3
. v
J
2
Figure 15.21 TB0MR to TB5MR Registers
0
C
1
9
0 .
8 /
B
0
3
5
0
3
G
J
7
u
o r
0 -
. l
Timer Bi Mode Register
b7
u
NOTES:
0
1
p
, 1
0
b6
3
1. MR0 and MR1 bit settings are enabled when the TCK1 bit is set to "0". The MR1 bit can be set to
2. j=i – 1, except j=2 when i=0 and j=5 when i=3.
(
2
M
0
either "0" or "1", when the TCK1 bit is set to "1".
b5
0
3
0
5
2
b4
C
8 /
Page 176
b3
, 5
b2
M
3
b1
0 1
2
C
b0
f o
8 /
4
5
TMOD0
TMOD1
Symbol
9
) T
TCK0
TCK1
MR0
MR2
MR3
4
MR1
Bit
Symbol
TB0MR to TB5MR 035B
(i=0 to 5)
Disabled in event counter mode. When write, set to "0".
When read, its content is indeterminate.
Disabled in event counter mode.
Can be set to "0" or "1".
Operating Mode
Select Bit
Count Polarity Select
Bit
TB0MR and TB3MR registers:
Set to "0" in event counter mode
TB1MR, TB2MR, TB4MR and TB5MR registers:
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Event Clock
Select Bit
(1)
Bit Name
(Event Counter Mode)
Address
16
, 035C
16
b3b2
, 035D
b1b0
0 0 : Counts falling edges of external signal
0 1 : Counts rising edges of external signal
1 0 : Counts falling and rising edges of
1 1 : Do not set to this value
0 : Input signal from the TBi
1 : TBj overflows
0 1 : Event counter mode
external signal
16
, 031B
16
Function
, 031C
(2)
16
, 031D
IN
16
pin
After reset
00XX 0000
15. Timer (Timer B)
RW
RW
RW
RW
RW
RW
RW
RW
2
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