M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 392

• Manufacturer Part Number: M30853FJGP#U3
• Description: IC M32C MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30853FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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23.4.2.1 When the INTSEL Bit is Set to "0"
If the CAN-associated interrupt is generated by one of the interrupt request source listed in 23.4.2
CANij Interrupts, the corresponding bit in the CiSISTR register (i=0,1) is set to "1" (interrupt re-
quested) when the CANi slot k completes a transmission or a reception. The corresponding bit in the
CiEISTR register is set to "1" (interrupt requested) when the CANi module detects a bus error, moves
into an error-passive state, or moves into a bus-off state.
The CANi interrupt request signal is set to "1" when the corresponding bit in the CiSISTR or CiEISTR
is set to "1" and the corresponding bit in the CiSIMKR or CiEIMKR is set to "1"
When the CAN0 interrupt request signal changes "0" to "1", all CAN0jR bits (j=0 to 2) in the IIO9IR to
IIO11IR registers are set to "1" (interrupt requested).
If at least one of the CAN0jE bits in the IIO9IE to IIO11IE registers is set to "1" (interrupt enabled), the
IR bits in the corresponding CAN0IC to CAN2IC registers are set to "1" (interrupt requested). The
CAN0 interrupt request signal remains set to "1" if another interrupt request source causes a corre-
sponding bit in the C0SISTR or C0EISTR to be set to "1" and the corresponding bit in the C0SIMKR or
C0EIMKR to be set to "1" after the CAN0 interrupt request signal changes "0" to "1". The CAN0jR and
IR bits also remain unchanged.
When the CAN1 interrupt request signal changes "0" to "1", all three CAN1jR bits in the IIO0IR to
IIO1IR and IIO5IR registers are set to "1" (interrupt requested).
If at least one of the CAN1jE bits in the IIO0IE to IIO1IE and IIO5IE registers is set to "1", the IR bits in
the corresponding CAN3IC to CAN5IC registers are set to "1". The CAN0 interrupt request signal
remains set to "1" if another interrupt request causes the corresponding bit in the C1SISTR or
C1EISTR to be set to "1" and the corresponding bit in the C1SIMKR or C1EIMKR to be set to "1" after
the CAN1 interrupt request signal changes "0" to "1". The CAN1jR and IR bits also remain unchanged.
Bits in the CiSISTR or CiEISTR register and CANijR bits (i=0,1, j=0 to 2) in the IIO0IR to IIO1IR, IIO5IR
or IIO9IR to IIO11IR registers are not set to "0" automatically, interrupt acknowledgment notwithstand-
ing. Set these bits to "0" by program.
The CANi interrupts are acknowledged when the CANijR bit in the IIO0IR to IIO1IR, IIO5IR or IIO9IR to
IIO11IR register and the corresponding bit in the CiSISTR or CiEISTR register are set to "0". If these
bits remain set to "1", all CAN-associated interrupt request source become invalid.
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23. CAN Module