M30622SAFP#U5 Renesas Electronics America, M30622SAFP#U5 Datasheet - Page 573

• Manufacturer Part Number: M30622SAFP#U5
• Description: IC M16C MPU ROMLESS 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30622SAFP#U5

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Appendix 1
2-254
Appendix 1 Check Sheet
The following check sheet was created based on items which had been the source of problems in the past.
We recommend you refer to the check sheet when troubleshooting.
Checks regarding register initial settings
Checks regarding the internal memory
Checks regarding the protect register
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Has the initial setting been made in the interrupt stack pointer (ISP) at the top of the program?
Has the initial setting been made in the user stack pointer (USP)? (Only if using the USP)
Does the USP overlap the ISP area? (Only if using the USP)
Is interrupt enabled after setting the ISP and USP?
Is the top address of the variable interrupt vector table set in the interrupt table register (INTB)?
Is interrupt enabled after setting the INTB?
Has the initial setting been made in the frame base register (FB)? (Only if using the FB)
Has the initial setting been made in the stack base register (SB)? (Only if using the SB)
Does the RAM capacity used in the program exceed the RAM capacity of the microcomputer?
Does the ROM capacity used in the program exceed the ROM capacity of the microcomputer?
Is writing enabled in the protect register (address 000A
register (addresses 0006
Is writing enabled in the protect register before writing in the processor mode register (addresses
0004
Is writing enabled in the protect register before writing in the port P9 direction register (address
03F3
Is writing effectuated in the port P9 direction register by the next instruction after writing is enabled in
the protect register?
Does not an interrupt generate between the instruction writing is enabled in the protect register and
the instruction writing in the port P9 direction register?
16
16
)?
and 0005
16
)?
16
and 0007
16
)?
16
) before writing in the system clock control
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M16C / 62A Group
Mitsubishi microcomputers