M30622SAFP#U5 Renesas Electronics America, M30622SAFP#U5 Datasheet - Page 203
![IC M16C MPU ROMLESS 100QFP](/photos/12/19/121993/m30622safp_u5_sml.jpg)
M30622SAFP#U5
Manufacturer Part Number
M30622SAFP#U5
Description
IC M16C MPU ROMLESS 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.QSK-62P_PLUS.pdf
(103 pages)
2.M30622SAFPU5.pdf
(277 pages)
3.M30622SAFPU5.pdf
(617 pages)
4.M30622SAFPU5.pdf
(308 pages)
Specifications of M30622SAFP#U5
Core Processor
M16C/60
Core Size
16-Bit
Speed
16MHz
Connectivity
SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
50
Program Memory Type
ROMless
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-QFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- QSK-62P_PLUS PDF datasheet
- M30622SAFPU5 PDF datasheet #2
- M30622SAFPU5 PDF datasheet #3
- M30622SAFPU5 PDF datasheet #4
- Current page: 203 of 617
- Download datasheet (9Mb)
Timing (Vcc = 5V)
1-182
Switching characteristics (referenced to V
Table 1.23.21. Memory expansion mode and microprocessor mode
Note 2: This is standard value shows the timing when the output is off,
Note 3: Specify a product of -40°C to 85°C to use it.
Note 1: Calculated according to the BCLK frequency as follows:
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
d(BCLK-AD)
h(BCLK-AD)
h(RD-AD)
d(BCLK-CS)
h(BCLK-CS)
d(BCLK-ALE)
h(BCLK-ALE)
d(BCLK-DB)
h(BCLK-DB)
h(WR-AD)
d(BCLK-RD)
h(BCLK-RD)
d(BCLK-WR)
h(BCLK-WR)
d(DB-WR)
h(WR-DB)
Symbol
and doesn't show hold time of data bus.
Hold time of data bus is different by capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
by a circuit of the right figure.
For example, when V
of output “L” level is
td(DB – WR) =
Address output delay time
WR signal output hold time
Address output hold time (BCLK standard)
Chip select output delay time
Chip select output hold time (BCLK standard)
ALE signal output hold time
RD signal output hold time
WR signal output delay time
Data output delay time (BCLK standard)
Data output hold time (BCLK standard)
Data output hold time (WR standard)(Note2)
Address output hold time (RD standard)
Address output hold time (WR standard)
ALE signal output delay time
RD signal output delay time
Data output delay time (WR standard)
(with wait, accessing external memory)
t = –CR X ln (1 – V
t = – 30pF X 1k X ln (1 – 0.2V
= 6.7ns.
f(BCLK)
85
10
o
OL
Parameter
C (Note 3), CM15 = “1” unless otherwise specified)
9
= 0.2V
OL
– 40
/ V
CC
CC
, C = 30pF, R = 1k , hold time
CC
[ns]
)
= 5V, V
CC
/ V
SS
CC
= 0V at Topr = – 20
)
Measuring condition
Figure 1.23.1
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(Note1)
o
Min.
C to 85
– 4
Standard
4
4
0
0
4
0
0
0
M16C / 62A Group
o
Mitsubishi microcomputers
Max.
C / – 40
DBi
V
25
25
25
25
25
40
CC
o
= 5V
Unit
C to
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R
C
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