M30622SAFP#U5 Renesas Electronics America, M30622SAFP#U5 Datasheet - Page 477

• Manufacturer Part Number: M30622SAFP#U5
• Description: IC M16C MPU ROMLESS 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30622SAFP#U5

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

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Address Match Interrupt
2.12 Address Match Interrupt Usage
Figure 2.12.1. Unexecuted instructions and corresponding stacked addresses
2.12.1 Overview of the address match interrupt usage
The address match interrupt is used for correcting a ROM or for a simplified debugging-purpose monitor.
The following is an overview of the address match interrupt usage.
<Instructions whose address is added to by 2 when an address match interrupt occurs>
<Instructions whose address is added to by 1 when an address match interrupt occurs>
(1) Enabling/disabling the address match interrupt
(2) Timing of the address match interrupt
(3) Returning from an address match interrupt
(4) How to determine an address match interrupt
The address match interrupt enable bit can be used to enable and disable an address match interrupt.
It is affected neither by the processor interrupt priority level (IPL) nor the interrupt enable flag (I flag).
An interrupt occurs immediately before executing the instruction in the address indicated by the ad-
dress match interrupt register. Set the first address of the instruction in the address match interrupt
register. Setting a half address of an instruction or an address of tabulated data does not generate an
address match interrupt.
The first instruction of an interrupt routine does not generate an address match interrupt either.
The address put in the stack when an address match interrupt occurs depends on the instruction not
yet executed (the instruction the address match interrupt register indicates). The return address is not
put in the stack. For this reason, to return from an address match interrupt, either rewrite the content
of the stack and use the REIT instruction or use the POP instruction to restore the stack to the state as
it was before the interrupt occurred and return by use of a jump instruction.
Figure 2.12.1 shows unexecuted instructions and corresponding the stacked addresses.
Address match interrupts can be set at two different locations. However, both location will have the
same vector address. Therefore, it is necessary to determine which interrupt has occurred; address
match interrupt 0 or address match interrupt 1. Using the content of the stack, etc., determine which
interrupt has occurred according to the first part of the address match interrupt routine.
• 16-bit operation code instructions
• 8-bit operation code instructions given below
• Instructions other than those listed above
ADD.B:S
OR.B:S
STNZ.B:S
CMP.B:S
JMPS
MOV.B:S
#IMM8,dest
#IMM8,dest
#IMM8,dest
#IMM8,dest
#IMM8
#IMM,dest (However, dest = A0/A1)
SUB.B:S
MOV.B:S
STZX.B:S
PUSHM
JSRS
#IMM8,dest
#IMM8,dest
#IMM81,#IMM82,dest
src
#IMM8
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
AND.B:S
STZ.B:S
POPM
M16C / 62A Group
Mitsubishi microcomputers
#IMM8,dest
#IMM8,dest
dest