MC908AP32CFAE Freescale Semiconductor, MC908AP32CFAE Datasheet - Page 120

• Manufacturer Part Number: MC908AP32CFAE
• Description: IC MCU 32K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AP32CFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, IRSCI, SCI, SPI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 32
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Monitor Mode (MON)
8.3.3 Break Signal
A start bit (logic 0) followed by nine logic 0 bits is a break signal. When the monitor receives a break signal,
it drives the PTA0 pin high for the duration of two bits and then echoes back the break signal.
8.3.4 Baud Rate
The communication baud rate is controlled by the crystal frequency and the state of the PTB0 pin (when
IRQ1 is set to V
PTB0 pin is at logic 0 upon entry into monitor mode, the divide by ratio is 512.
If monitor mode was entered with V
This condition for monitor mode entry requires that the reset vector is blank.
Table 8-3
standard baud rates can be accomplished using proportionally higher or lower frequency generators. If
using a crystal as the clock source, be aware of the upper frequency limit that the internal clock module
can handle.
8.3.5 Commands
The monitor ROM firmware uses these commands:
The monitor ROM firmware echoes each received byte back to the PTA0 pin for error checking. An 11-bit
delay at the end of each command allows the host to send a break character to cancel the command. A
delay of two bit times occurs before each echo and before READ, IREAD, or READSP data is returned.
The data returned by a read command appears after the echo of the last byte of the command.
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READ (read memory)
WRITE (write memory)
IREAD (indexed read)
IWRITE (indexed write)
READSP (read stack pointer)
RUN (run user program)
lists external frequencies required to achieve a standard baud rate of 9600 BPS. Other
TST
4.9152 MHz
9.8304 MHz
9.8304 MHz
Frequency
External
) upon entry into monitor mode. When PTB0 is high, the divide by ratio is 1024. If the
0
1
2
MISSING STOP BIT
3
Table 8-3. Monitor Baud Rate Selection
MC68HC908AP A-Family Data Sheet, Rev. 3
4
DD
IRQ1
V
V
V
Figure 8-4. Break Transaction
TST
TST
DD
5
on IRQ1, then the divide by ratio is set at 1024, regardless of PTB0.
6
7
PTB0
X
0
1
2-STOP BIT DELAY BEFORE ZERO ECHO
2.4576 MHz
2.4576 MHz
2.4576 MHz
Frequency
Internal
0
1
2
3
4
Baud Rate
5
(BPS)
9600
9600
9600
6
Freescale Semiconductor
7