ADUC7024BSTZ62 Analog Devices Inc, ADUC7024BSTZ62 Datasheet - Page 63

• Manufacturer Part Number: ADUC7024BSTZ62
• Description: IC MCU FLASH 62K ANLG I/O 64LQFP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7024BSTZ62

• Core Size: 16/32-Bit
• Program Memory Size: 62KB (62K x 8)
• Design Resources: Sensing Low-g Acceleration Using ADXL345 Digital Accelerometer Connected to ADuC7024 (CN0133)
• Core Processor: ARM7
• Speed: 44MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: PLA, PWM, PSM, Temp Sensor, WDT
• Number Of I /o: 30
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 10x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LQFP
• Controller Family/series: (ARM7) ADUC
• No. Of I/o's: 30
• Ram Memory Size: 8KB
• Cpu Speed: 44MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, SPI, UART
• Rohs Compliant: Yes
• Package: 64LQFP
• Device Core: ARM7TDMI
• Family Name: ADuC7xxx
• Maximum Speed: 44 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 30
• Interface Type: I2C/SPI/UART
• On-chip Adc: 10-chx12-bit
• On-chip Dac: 2-chx12-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Normal 450 UART Baud Rate Generation
The baud rate is a divided version of the core clock using the value
in the COMDIV0 and COMDIV1 MMRs (16-bit value, DL).
Table 48 gives some common baud rate values.
Table 48. Baud Rate Using the Normal Baud Rate Generator
Baud Rate
9,600
19,200
115,200
9,600
19,200
115,200
The Fractional Divider
The fractional divider, combined with the normal baud rate
generator, produces a wider range of more accurate baud rates.
Calculation of the baud rate using fractional divider is as follows:
For example, generation of 19,200 baud with CD bits = 3
(Table 48 gives DL = 0x08), is
where:
M = 1
N = 0.06 × 2048 = 128
where:
Baud Rate = 19,200 bps
Error = 0%, compared to 6.25% with the normal baud rate
generator.
Baud
Baud
Baud
M
M
M
+
+
+
CLOCK
CORE
2048
2048
2048
Rate
Rate
Rate
N
N
N
Figure 62. Baud Rate Generation Options
CD
0
0
0
3
3
3
=
=
=
/(M+N/2048)
=
=
=
. 1
19200
Baud
2
2
2
06
CD
3
/2
CD
×
41
DL
0x88
0x44
0x0B
0x11
0x08
0x01
×
16
×
41
.
41
Rate
78
16
16
×
×
.
78
2
.
8
MHz
×
78
×
3
41
×
41
FBEN
MHz
DL
×
2
×
MHz
2
.
16
×
Actual Baud Rate
9,600
19,200
118,691
9600
20,400
163,200
78
.
×
78
2
DL
×
×
CD
⎛
⎜
⎝
MHz
2
MHz
8
2048
×
128
×
×
⎛
⎜
⎝
2
M
16
/16DL
⎞
⎟
⎠
+
×
DL
2048
N
×
2
⎞
⎟
⎠
UART
% Error
0
0
3
0
6.25
41.67
Rev. B | Page 63 of 92
UART Register Definitions
The UART interface consists of 12 registers: COMTX, COMRX,
COMDIV0, COMIEN0, COMDIV1, COMIID0, COMCON0,
COMCON1, COMSTA0, COMSTA1, COMSCR, and
COMDIV2.
COMTX Register
Name
COMTX
COMTX is an 8-bit transmit register.
COMRX Register
Name
COMRX
COMRX is an 8-bit receive register.
COMDIV0 Register
Name
COMDIV0
COMDIV0 is a low byte divisor latch. COMTX, COMRX,
and COMDIV0 share the same address location. COMTX
and COMRX can be accessed when Bit 7 in COMCON0
register is cleared. COMDIV0 can be accessed when Bit 7
of COMCON0 is set.
COMIEN0 Register
Name
COMIEN0
COMIEN0 is the interrupt enable register.
Table 49. COMIEN0 MMR Bit Descriptions
Bit
7:4
3
2
1
0
COMDIV1 Register
Name
COMDIV1
COMDIV1 is a divisor latch (high byte) register.
COMIID0 Register
Name
COMIID0
COMIID0 is the interrupt identification register.
ADuC7019/20/21/22/24/25/26/27/28
Name
–
EDSSI
ELSI
ETBEI
ERBFI
Address
0xFFFF0700
Address
0xFFFF0700
Address
0xFFFF0700
Address
0xFFFF0704
Address
0xFFFF0704
Address
0xFFFF0708
Description
Reserved.
Modem Status Interrupt Enable Bit. Set by
user to enable generation of an interrupt if
any of COMSTA1[3:1] are set. Cleared by user.
Rx Status Interrupt Enable Bit. Set by user to
enable generation of an interrupt if any of
COMSTA0[3:0] are set. Cleared by user.
Enable Transmit Buffer Empty Interrupt. Set
by user to enable interrupt when buffer is
empty during a transmission. Cleared by user.
Enable Receive Buffer Full Interrupt. Set by
user to enable interrupt when buffer is full
during a reception. Cleared by user.
Default Value
0x00
Default Value
0x00
Default Value
0x00
Default Value
0x00
Default Value
0x00
Default Value
0x01
Access
R/W
Access
R
Access
R/W
Access
R/W
Access
R/W
Access
R