ADUC7024BSTZ62 Analog Devices Inc, ADUC7024BSTZ62 Datasheet - Page 53

• Manufacturer Part Number: ADUC7024BSTZ62
• Description: IC MCU FLASH 62K ANLG I/O 64LQFP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7024BSTZ62

• Core Size: 16/32-Bit
• Program Memory Size: 62KB (62K x 8)
• Design Resources: Sensing Low-g Acceleration Using ADXL345 Digital Accelerometer Connected to ADuC7024 (CN0133)
• Core Processor: ARM7
• Speed: 44MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: PLA, PWM, PSM, Temp Sensor, WDT
• Number Of I /o: 30
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 10x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LQFP
• Controller Family/series: (ARM7) ADUC
• No. Of I/o's: 30
• Ram Memory Size: 8KB
• Cpu Speed: 44MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, SPI, UART
• Rohs Compliant: Yes
• Package: 64LQFP
• Device Core: ARM7TDMI
• Family Name: ADuC7xxx
• Maximum Speed: 44 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 30
• Interface Type: I2C/SPI/UART
• On-chip Adc: 10-chx12-bit
• On-chip Dac: 2-chx12-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

MMRs and Keys
The operating mode, clocking mode, and programmable clock
divider are controlled via two MMRs, PLLCON (see Table 33)
and POWCON (see Table 34). PLLCON controls the operating
mode of the clock system, while POWCON controls the core
clock frequency and the power-down mode.
To prevent accidental programming, a certain sequence (see
Table 35) has to be followed to write to the PLLCON and
POWCON registers.
PLLKEYx Registers
Name
PLLKEY1
PLLKEY2
PLLCON Register
Name
PLLCON
Table 33. PLLCON MMR Bit Designations
Bit
7:6
5
4:2
1:0
POWKEYx Registers
Name
POWKEY1
POWKEY2
Value
00
01
10
11
Name
OSEL
MDCLK
Address
0xFFFF0410
0xFFFF0418
Address
0xFFFF0414
Address
0xFFFF0404
0xFFFF040C
Description
Reserved.
32 kHz PLL Input Selection. Set by
user to select the internal 32 kHz
oscillator. Set by default. Cleared by user
to select the external 32 kHz crystal.
Reserved.
Clocking Modes.
Reserved.
PLL. Default configuration.
Reserved.
External Clock on P0.7 Pin.
Default Value
0x0000
0x0000
Default Value
0x21
Default Value
0x0000
0x0000
Access
W
W
Access
R/W
Access
W
W
Rev. B | Page 53 of 92
POWCON Register
Name
POWCON
Table 34. POWCON MMR Bit Designations
Bit
7
6:4
3
2:0
Table 35. PLLCON and POWCON Write Sequence
PLLCON
PLLKEY1 = 0xAA
PLLCON = 0x01
PLLKEY2 = 0x55
ADuC7019/20/21/22/24/25/26/27/28
Value
000
001
010
011
100
Others
000
001
010
011
100
101
110
111
Address
0xFFFF0408
Name
PC
CD
Description
Reserved.
Operating Modes.
Active Mode.
Pause Mode.
Nap.
Sleep Mode. IRQ0 to IRQ3 and Timer2
can wake up the part.
Stop Mode. IRQ0 to IRQ3 can wake
up the part.
Reserved.
Reserved.
CPU Clock Divider Bits.
41.78 MHz.
20.89 MHz.
10.44 MHz.
5.22 MHz.
2.61 MHz.
1.31 MHz.
653 kHz.
326 kHz.
Default Value
0x0003
POWCON
POWKEY1 = 0x01
POWCON = User Value
POWKEY2 = 0xF4
Access
R/W