ADUC702 AD [Analog Devices], ADUC702 Datasheet
ADUC702
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ADUC702 Summary of contents
Page 1
... SERIAL I/O 4 GEN. PUR- POR JTAG UART, SPI POSE TIMERS Figure 1 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.326.8703 ADuC702x Series 3mA (@1MHz) 50mA (@45MHz) (See general description on page 11) 12-BIT DAC DAC0 12-BIT DAC DAC1 12-BIT DAC DAC2 ...
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... Three-phase PWM..................................................................... 42 General Purpose I/O.................................................................. 49 Serial Port Mux........................................................................... 52 Programmable Logic Array (PLA)........................................... 62 Processor reference peripherals.................................................... 65 Interrupt System ......................................................................... 65 Timers .......................................................................................... 67 ADuC702x Hardware Design considerations ............................ 75 Power supplies ............................................................................ 75 Grounding and Board Layout Recommendations................. 75 Clock Oscillator .......................................................................... 76 Power-on reset operation .......................................................... 76 Typical sysem configuration ..................................................... 77 Development Tools ........................................................................ 78 In-Circuit Serial Downloader................................................... 78 Outline Dimensions ...
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... Bits ±2 LSB typ ±1 LSB max ±2 mV max ±5 mV max ±0.5 % max TBD % typ Rev. PrB | Page ADuC702x Series = 45MHz, All specifications MAX Test Conditions/Comments f = 1MSPS SAMPLE 2.5V internal reference 2.5V internal reference 1.0V external reference 2.5V internal reference 2.5V internal reference 1.0V external reference ...
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... ADuC702x Series Parameter ANALOG OUTPUTS Output Voltage Range_0 Ouput Voltage Range_1 Output Voltage Range_2 Output Impedance DAC AC CHARACTERISTICS Voltage Output Settling Time Voltage Output Settling Time Digital to Analog Glitch Energy COMPARATOR Input Offset Voltage Input Bias Current Input Voltage Range Input Capacitance ...
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... ADC voltage input range specified. CM Rev. PrB | Page ADuC702x Series Test Conditions/Comments 1MHz clock 1MHz clock 45MHz clock 45MHz clock External Crystal or Internal Osc ON External Crystal or Internal Osc ON ...
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... ADuC702x Series TERMINOLOGY ADC Specifications Integral Nonlinearity This is the maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point 1/2 LSB below the first code transition and full scale, a point 1/2 LSB above the last code transition ...
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... Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. = 25°C unless otherwise noted Rating -0.3V to +0.3V -0.3V to +0.3V -0.3V to +7V -0.3V to +5.5V -0.3V to +5.5V -0.3V to AVDD+0.3V -0.3V to AVDD+0.3V –40°C to +125°C TBD 125°C TBD TBD TBD TBD Rev. PrB | Page ADuC702x Series = IOV , AGND = REFGND = DACGND = DD DD ...
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... ADuC702x Series PIN CONFIGURATION 40-Lead CSP 40 PIN 1 1 IDENTIFIER ADuC7020/21/22 TOP VIEW (Not to Scale 64-Lead CSP 64 PIN 1 1 IDENTIFIER ADuC7024/ADuC7025 TOP VIEW (Not to Scale Rev. PrB | Page Preliminary Technical Data 64-Lead LQFP 64 49 ...
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... Phase 62kB/8kB Three Yes 40 Phase 62kB/8kB Three Yes 40 Phase 62kB/8kB Three Yes 40 Phase Rev. PrB | Page ADuC702x Series Temp Package Package Range Description Option –40° 40-Lead Chip CP-40 85°C Scale Package –40° 40-Lead Chip CP-40 85°C Scale Package –40° ...
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... JTAG Test Port Input - Test Mode Select. Debug and download access I JTAG Test Port Input – Test Data In. Debug and download access Multifunction I/O pin: Boot Mode. The ADuC702X will enter serial download mode low /P OUT I/O at reset and will execute code pulled high at reset through a 1kOhm resistor/ General Purpose Input-Output Port 0 ...
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... General Purpose Input-Output Port 4.2 / Programmable Logic Array I/O Output Element 10 2.5V internal Voltage Reference. Must be connected to a 0.47uF capacitor I/O when using the internal reference. S Analog Ground. Ground reference point for the analog circuitry S 3.3V Analog Power Rev. PrB | Page ADuC702x Series 2 C1 /Programmable 2 C1 /Programmable Programmable ...
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... General Purpose Input-Output Port 4.7/ Programmable Logic Array Output I/O Element 15 Multifunction I/O pin: Boot Mode. The ADuC7024/ADuC7025 will enter download mode low I/O at reset and will execute code pulled high at reset through a 1kOhm resistor/ General Purpose Input-Output Port 0.0 / Voltage Comparator Output/ Programmable Logic Array Input Element 7 ...
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... Array Input Element 1 Serial Port Multiplexed: I/O General Purpose Input-Output Port 1.0/ Timer 1 Input / UART / I Programmable Logic Array Input Element 0 General Purpose Input-Output Port 4.2 / Programmable Logic Array Output I/O Element 10 Rev. PrB | Page ADuC702x Series 2 C1 /Programmable Logic 2 C1 /Programmable Logic Programmable Logic ...
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... DD 61 ADC0 62 ADC1 63 ADC2/CMP0 64 ADC3/CMP1 * I = Input Output Supply. ** DAC outputs not present on ADuC7025 * Type Function General Purpose Input-Output Port 4.3 / Programmable Logic Array Output I/O Element 11 General Purpose Input-Output Port 4.4 / Programmable Logic Array Output I/O Element 12 General Purpose Input-Output Port 4.5 / Programmable Logic Array Output ...
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... General Purpose Input-Output Port 4.7/ External Memory Interface / I/O Programmable Logic Array Output Element 15 Multifunction I/O pin: Boot Mode. The ADuC7026 will enter UART download mode low at I/O reset and will execute code pulled high at reset through a 1kOhm resistor/ General Purpose Input-Output Port 0.0 / Voltage Comparator ...
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... ADuC702x Series Pin# Mnemonic 34 P0.3/TRST/A16/ADC BUSY 35 P2.5/MS1 36 P2.6/MS2 37 RST 38 P3.4/AD4/PWM2 /PLAI[12 P3.5/AD5/PWM2 /PLAI[13 IRQ0/P0.4/CONV /PLAO[1] START 41 IRQ1/P0.5/ADC /PLAO[2] BUSY 42 P2.0/PWM /SPM9/PLAO[5]/CONV TRIP 43 P0.7/ECLK/SPM8/PLAO[4]/XCLK 44 XCLKO 45 XCLKI 46 P3.6/AD6/PWM /PLAI[14] TRIP 47 P3.7/AD7/ECLK/PLAI[15] 48 P2.7/MS3 49 P2.1/WS 50 P2.2/RS 51 P1.7/SPM7/PLAO[0] 52 P1.6/SPM6/PLAI[6] 53 IOGND 54 IOV ...
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... Single-ended or differential Analog input 11 I Single-ended or differential Analog input 0 I Single-ended or differential Analog input 1 I Single-ended or differential Analog input 2/ Comparator positive input I Single-ended or differential Analog input 3/ Comparator negative input Rev. PrB | Page ADuC702x Series 2 C1 /Programmable Logic 2 C1 /Programmable Logic Programmable Logic ...
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... ADuC702x Series ADC0 ADC1 ADC2/CMP0 ADC3/CMP1 ADC4 12-BIT SAR ADC5 ADC 1MSPS ADC6 MUX ADC7 ADC8 ADC9 ADC10 ADC11 TEMP ADC NEG SENSOR MUX DAC CMP BM/P0.0/CMP /PLAI OUT V REF DAC MUX V REF BAND GAP REFERENCE SPI/I P4.6/PLAO/AD14 INTERFACE PROG. LOGIC P4 ...
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... DAC output pins. The 4 DAC outputs are only available on certain models of the ADuC702x, though in many cases where the DAC is not present this pin can still be used as an additional ADC input, giving a maximum of 16 ADC input channels. The ADC can operate in single-ended or differential input modes ...
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... ADuC702x Series - Memory abort - Attempted execution of an undefined instruction - Software interrupt (SWI) instruction which can be used to make a call to an operating system. Typically the programmer will define interrupts as IRQ but for higher priority interrupt, i.e. faster response time, the programmer can define interrupt as FIQ. ...
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... The ARM7 core sees memory as a linear array byte location where the different blocks of memory are mapped as outlined in . Figure 4 The ADuC702x memory organisation is configured in little endian format: the least significant byte is located in the lowest byte address and the most significant byte in the highest byte address. bit0 ...
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... ADuC702x Series 0xFFFFFFFF 0xFFFFFC3C PWM 0xFFFFFC00 0xFFFFF820 Flash Control Interface 0xFFFFF800 0xFFFFF46C GPIO 0xFFFFF400 0xFFFF0B54 PLA 0xFFFF0B00 0xFFFF0A14 SPI 0xFFFF0A00 0xFFFF0948 0xFFFF0900 0xFFFF0848 0xFFFF0800 0xFFFF0730 UART 0xFFFF0700 0xFFFF0620 DAC 0xFFFF0600 0xFFFF0538 ADC 0xFFFF0500 0xFFFF0490 Bandgap Reference 0xFFFF048C 0xFFFF0448 Power Supply ...
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... Rev. PrB | Page ADuC702x Series Name Byte Access Type Cycle PLLCON PLLKEY2 PSMCON CMPCON REFCON ADCCON 1 RW ...
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... ADuC702x Series Address Name Byte Access Type I2C0 base address = 0xFFFF0800 0x0800 I2C0MSTA 1 R 0x0804 I2C0SSTA 1 R 0x0808 I2C0SRX 1 R 0x080C I2C0STX 1 W 0x0810 I2C0MRX 1 R 0x0814 I2C0MTX 1 W 0x0818 I2C0CNT 1 RW 0x081C I2C0ADR 1 RW 0x0824 I2C0BYTE 1 RW 0x0828 I2C0ALT 1 RW ...
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... Rev. PrB | Page ADuC702x Series ...
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... ADuC702x Series ADC CIRCUIT INFORMATION GENERAL OVERVIEW The Analog Digital Converter (ADC) incorporates a fast, multi- channel, 12-bit ADC. It can operate from 2.7V to 3.6V supplies and is capable of providing a throughput 1MSPS when the clock source is 45MHz. This block provides the user with multi-channel multiplexer, differential track-and-hold, on-chip reference and ADC ...
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... ADCRST: ADC Reset Register. Resets all the ADC registers their default value. - ADCOF: Offset calibration register. 10-bit register - ADCGN: Gain calibration register. 10-bit register Table 7: ADCCON MMR Bit Designations pin BUSY pin BUSY Rev. PrB | Page ADuC702x Series ...
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... ADuC702x Series 000 Enable CONV pin as a conversion input START 001 Enable timer conversion input 010 Enable timer conversion input 011 Single software conversion, will be set to 000 after conversion. 100 Continuous software conversion 101 PLA conversion Other Reserved Table 8: ADCCP* MMR bit designation ...
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... REF AIN11 Figure 12: ADC conversion phase Pseudo-differential mode In pseudo-differential mode, Channel- is linked to the VIN- pin of the ADuC702x and SW2 switches between A (Channel-) and B (VREF). VIN- pin must be connected to Ground or a low voltage. The input signal REF not exceed AV AIN0 ...
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... ADC channel input) facilitating an internal temperature to an accuracy of ±3°C. BANDGAP REFERENCE The ADuC702x provides an on-chip bandgap reference of 2.5V, which can be used for the ADC and for the DAC. This internal reference also appears on the V reference, a capacitor of 0.47µF must be connected from the external V during ADC conversions ...
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... Set by user to connect the internal 2.5V reference to the VREF pin. The reference can be used for external component but will need to be buffered. Cleared by user to disconnect the reference from the VREF pin. Table 11: REFCON MMR bit designations Rev. PrB | Page ADuC702x Series ...
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... Serial Downloading (In-Circuit Programming) The ADuC702x facilitates code download via the standard UART serial port or via the I2C port. The ADuC702x will enter serial download mode after a reset or power cycle if the BM pin is pulled low through an external 1kOhm resistor. Once in serial ...
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... FEEPRO: protection following subsequent reset MMR. Requires software key. See description Table 15 - FEEHIDE: Immediate Protection MMR. Does not require any software keys. See description Table 15 Table 12: FEESTA MMR bit designations Table 13: FEEMOD MMR bit designations Table 14: command codes in FEECON Rev. PrB | Page ADuC702x Series ...
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... ADuC702x Series Mass erase Erase 62kByte of user space. The 2kByte of kernel are protected. This operation takes 2.48s To prevent 0x06* accidental execution a command sequence is required to execute this instruction, this is described below. 0x07 Burst read Default command. No write is allowed. This operation takes 2 cycles Write can handle a maximum of 8 data of 16 bits and takes a maximum µ ...
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... With 1<N≤16, N number of data to load or store in the multiple time load/store instruction. 1 The SWAP instruction combine a LD and STR instruction with 1 only one fetch giving a total of 8 cycles plus 40µs. Rev. PrB | Page ADuC702x Series 20µ 20µs ...
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... When a reset occurs on the ADuC702x, execution starts automatically in factory programmed internal configuration code. This so called kernel is hidden and cannot be accessed by user code. If the ADuC702x is in normal mode (BM pin is FFFFFFFFh high), it will execute the power-on configuration routine of the kernel and then jump to the reset vector address, 0x00000000, to execute the users reset exception routine ...
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... Preliminary Technical Data OTHER ANALOG PERIPHERALS DAC The ADuC702x incorporate dual 12-bit voltage output DACs on-chip. Each DAC has a rail-to-rail voltage output buffer capable of driving 5kΩ/100pF. Each buffer can be bypassed. Each DAC has three selectable ranges bandgap 2.5V reference DAC AV ...
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... DAC0 The endpoint nonlinearities conceptually illustrated in Figure 18 get worse as a function of output loading. Most of the ADuC702x’s datasheet specifications assume a 5 kΩ resistive load to ground at the DAC output. As the output is forced to source or sink more current, the nonlinear regions at the top or bottom (respectively) of Figure 18 become larger. ...
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... A write of ‘0’ has no effect. There is no timeout delay, PSMI may be cleared immediately once CMP goes high. COMPARATOR The ADuC702x also integrates an uncommitted voltage comparator. The positive input is multiplexed with ADC2 and the negative input has two options: ADC3 or DAC0. The output of the ...
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... PLL clock divided 5.6 MHz. The core clock frequency can be output on the ECLK pin as described Figure 20. A power down mode is available on the ADuC702x. The operating mode, clocking mode and programmable clock divider are controlled via two MMRs, PLLCON and POWCON. ...
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... Reserved PLL + 32kHz oscillator – default configuration Reserved XCLK pin Table 24: POWCON MMR bit designations Normal mode Power down mode enable. XIRQ0, XIRQ1, timer2 and timer3 can wake-up the ADuC702x. Reserved 45.088 MHz 22.544 MHz 11.272 MHz 5.636 MHz 2.818 MHz 1 ...
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... PWM outputs. The size of the pulse on the SYNC pin must be greater than two core clock periods. The PWM signals produced by the ADuC702x can be shut off via a dedicated asynchronous PWM shutdown pin, PWMTRIP, that, when brought low, instantaneously places all six PWM outputs in the OFF state (high) ...
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... The PWM sync pulse control unit generates the internal synchronisation pulse and also controls whether the external SYNC pin is used or not. The PWM controller is driven by the ADuC702x core clock frequency and is capable of generating two interrupts to the ARM core. One interrupt is generated on the occurrence of a PWMSYNC pulse and the other is generated on the occurrence of any PWM shutdown action ...
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... MHz. Obviously, the dead time can be programmed to be zero by writing 0 to the PWMDAT1 register. PWM Operating Mode, PWMCON and PWMSTA MMRs The PWM controller of the ADuC702x can operate in two distinct modes, single update mode and double update mode. The operating mode of the PWM controller is determined by the state of Bit 2 of the PWMCON register ...
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... Output Control Unit so that the signal will ultimately appear at the 0L – PWMDAT1 ) 1 2 pin. Of course, the corresponding low-side output of the Timing Unit is also diverted to the complementary high-side output of Rev. PrB | Page ADuC702x Series + PWMDAT0 - PWMCH0 1 2 – PWMDAT1 ) ...
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... ADuC702x Series the Output Control Unit so that the signal appears at the 0H pin. Following a reset, the three crossover bits are cleared so that the crossover mode is disabled on all three pairs of PWM signals. The PWMEN register also contains six bits (Bits that can be used to individually enable or disable each of the six PWM outputs ...
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... PWMCH0,CH1,CH2: channel duty cycle for the three phases - PWMEN: allows enabling channel outputs and crossover. See bit definition Table 28. - PWMDAT2: unsigned 10-bit register for PWM sync pulse width. Table 25: PWMCON MMR Bit Descriptions Table 26: PWMSTA MMR Bit Descriptions Rev. PrB | Page ADuC702x Series ...
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... ADuC702x Series 8 PWMTRIPINT PWM trip interrupt bit 3 PWMTRIP Raw signal from the PWMTRIP pin 2-1 Reserved 0 PWMPHASE PWM Phase Bit Set to ‘1’ by the MicroConverter when the timer is counting down (1 Clear to ‘0’ by the MicroConverter when the timer is counting up (2 Bit Name ...
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... Preliminary Technical Data GENERAL PURPOSE I/O The ADuC702x provides 40 General Purpose bi-directional I/O pins (GPIO). All I/O pins are 5V tolerant which means that the GPIOs support an input voltage of 5V. In general many of the GPIO pins have multiple functions, see Table 30 for the pin function definition. By default the GPIO pins are configured in GPIO mode ...
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... ADuC702x Series GPIO - P4.7 AD15 PLAO[15] Rev. PrB | Page Preliminary Technical Data ...
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... Set to ‘1’ by the user to clear bit on port x, will also clear the corresponding bit in the GPxDAT MMR Clear to ‘0’ by the user will not affect the data out 15-0 Reserved Table 31: GPxDAT MMR Bit Descriptions Table 32: GPxSET MMR Bit Descriptions Table 33: GPxCLR MMR Bit Descriptions Rev. PrB | Page ADuC702x Series ...
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... MODEM, and parallel-to-serial conversion on data characters received from the CPU. The UART includes a fractional divider for baudrate generation and has a network addressable mode. The UART function is made available on the following 10 pins of the ADuC702x: Pin Signal Description SPM0 (mode 1) ...
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... COMIID0: interrupt identification register - COMCON1: modem control register - COMSTA1: modem status register - COMDIV2: 16-bit fractional baud divide register - COMSCR: 8-bit scratch register used for temporary storage. Also used in network addressable UART mode. Table 37: COMCON0 MMR Bit Descriptions Rev. PrB | Page ADuC702x Series ...
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... ADuC702x Series Bit Name Description 7 Reserved 6 TEMT COMTX empty status bit Set automatically if COMTX is empty Cleared automatically when writing to COMTX 5 THRE COMTX and COMRX empty Set automatically if COMTX and COMRX are empty Cleared automatically when one of the register receives data 4 BI ...
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... Set by user to enable the fractional baudrate generator Cleared by user to generate baudrate using the standard 450 UART baudrate generator 14-13 Reserved 12-11 FBM[1- FBM = 10-0 FBN[10-0] N Table 41: COMCON1 MMR Bit Descriptions Table 42: COMSTA1 MMR Bit Descriptions Table 43: COMDIV2 MMR Bit Descriptions Rev. PrB | Page ADuC702x Series ...
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... ADuC702x Series Network addressable UART mode This mode allows connecting the MicroConverter on a 256- node serial network, either as a hardware single-master or via software in a multi-master network. Bit 7 of COMIEN1 (ENAM bit) must be set to enable UART in network addressable mode. Note that there is no parity check in this mode, the parity bit is used for address ...
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... Preliminary Technical Data SERIAL PERIPHERAL INTERFACE The ADuC702x integrates a complete hardware Serial Peripheral Interface (SPI) on-chip. SPI is an industry standard synchronous serial interface that allows eight bits of data to be synchronously transmitted and received simultaneously, i.e., full duplex maximum bit rate of 5.6Mbs. The SPI Port can ...
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... ADuC702x Series Cleared by user, the new serial byte received is discarded 7 SPITX underflow mode Set by user to transmit the previous data Cleared by user to transmit 0 6 Transfer and interrupt mode (master mode) Set by user to initiate transfer with a write to the SPITX register. Interrupt will occur when TX is empty Cleared by user to initiate transfer with a read of the COMRX register ...
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... Preliminary Technical Data COMPATIBLE INTERFACES The ADuC702x supports two fully licensed interfaces are both implemented as a full hardware master and 2 slave interface. The two I C interfaces being identical, this 2 document will describe only detail. The two pins used for data transfer, SDA and SCL are configured in a Wired-AND format that allows arbitration in a multi-master system ...
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... ADuC702x Series 3 General call enable bit Set by user to address every device on the I Cleared by user to operate in normal mode 2 Reserved 1 Master enable bit Set by user to enable the master I Cleared by user to disable the master I 0 Slave enable bit Set by user to enable the slave I I2C0ID1, I2C0ID2 and I2C0ID3. if the device address is recognised the part will participate in the slave transfer sequence ...
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... Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser 2 under the Philips I C Patent Rights to use the ADuC702X provided that the system conforms to the I defined by Philips system Standard Specification as Rev. PrB | Page ...
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... Figure 27: PLA element In total, 30 GPIO pins are available on the ADuC702x for the PLA. These include 16 input pins and 14 output pins. They need to be configured in the GPxCON register as PLA pins before using the PLA. Note that the comparator output is also included as one of the 16 input pins ...
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... PLA element 1 … 1111 – PLA element 15 7-5 Reserved 4 PLA IRQ0 enable bit Set by user to enable IRQ0 output from PLA Cleared by user to disable IRQ0 output from PLA Table 53: PLACLK MMR Bit Descriptions Table 54: PLAIRQ MMR Bit Descriptions Rev. PrB | Page ADuC702x Series ...
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... ADuC702x Series 3-0 PLA IRQ0 source 0000 – PLA element 0 0001 – PLA element 1 … 1111 – PLA element 15 Bit Description 31-5 Reserved 4 ADC start conversion enable bit Set by user to enable ADC start conversion from PLA Cleared by user to disable ADC start conversion from PLA ...
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... Preliminary Technical Data PROCESSOR REFERENCE PERIPHERALS INTERRUPT SYSTEM There are 24 interrupt sources on the ADuC702x which are controlled by the Interrupt Controller. Most interrupts are generated from the on-chip peripherals like ADC, UART, etc. and two additional interrupt sources are generated from external interrupt request pins, XIRQ0 and XIRQ1. The ...
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... ADuC702x Series registers at the same time. The 32-bit register dedicated to software interrupt is SWICFG described Table 59. This MMR allows the control of Bit Description 31-3 Reserved 2 Programmed Interrupt-FIQ Setting/clearing this bit correspond in setting/clearing bit 1 of FIQSTA and FIQSIG 1 Programmed Interrupt-IRQ Setting/clearing this bit correspond in setting/clearing bit 1 of IRQSTA and IRQSIG ...
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... Preliminary Technical Data TIMERS The ADuC702x has four general purpose Timer/Counters: - Timer0, - Timer1, - Timer2 or Wake-up Timer, - Timer3 or Watchdog Timer. The four timers in their normal mode of operation can be either free-running or periodic free-running mode the counter decrements/increments from the maximum/minimum value until zero/full scale and starts again at the maximum /minimum value ...
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... ADuC702x Series bit unsigned integers. T1VAL and T1CAP are read-only. - T1CLRI is an 8-bit register. Writing any value to this register will clear the timer1 interrupt. 32kHz Oscillator Core Clock Frequency P0.6 P1.0 Bit Description 31-18 Reserved 17 Event Select bit: Set by user to enable time capture of an event ...
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... T3LD. Timer3 is clocked by the internal 32kHZ crystal when operating in the Watchdog mode. If the timer reaches 0, a reset or an interrupt occurs, depending on bit 1 in T3CON register. To avoid reset or interrupt, any Rev. PrB | Page ADuC702x Series 32-bit Load Timer2IRQ Prescaler / 1, 16, 256 ...
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... ADuC702x Series value must be written to T3ICLR before the expiration period. This reloads the counter with T3LD and begins a new timeout period. As soon watchdog mode is entered, T3LD and T3CON are write-protected. These two registers can not be modified until a reset clears the watchdog enable bit and causes Timer3 to exit watchdog mode ...
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... Preliminary Technical Data External Memory Interfacing The only ADuC702x models which feature an external memory interface are the ADuC7026 and ADuC7027. The external memory interface requires a larger number of pins, this is why it is only available on larger pin count package. The pins required for interfacing to an external memory are: ...
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... ADuC702x Series Cleared by the user to enable one extra clock before and after the Read Strobe Extra bus transition time on Write Set by the user to disable extra bus transition time Cleared by the user to enable one extra clock before and after the Write Strobe, WS ...
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... Preliminary Technical Data MCLK ADDRESS AD 16:0 MSx Figure 34: External Memory Read Cycle MCLK ADDRESS AD 16:0 MSx Figure 35: External Memory Read cycle with Address hold and Bus turn cycles DATA DATA Rev. PrB | Page ADuC702x Series ...
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... ADuC702x Series MCLK ADDRESS AD 16:0 MSx Figure 36: External Memory Write Cycle with address and write hold cycles MCLK ADDRESS AD 16:0 MSx Figure 37: External Memory Write Cycle with wait states Preliminary Technical Data DATA DATA Rev. PrB | Page ...
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... ADuC702x must be referenced to the same system ground reference point. DD Linear Voltage regulator to be kept relatively free line. The ADuC702x requires a single 3.3V supply but the core logic DD requires a 2.5V supply. An on-chip linear regulator generates the 2.5V from IOV supply for the core logic. An external compensation capacitor of 0.47 µF must be connected between LV ...
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... ADuC702x’s digital inputs, add a series resistor to each relevant line to keep rise and fall times longer than the ADuC702x input pins. A value of 100Ω or 200Ω is usually sufficient to prevent high speed signals from coupling capacitively into the ADuC702x and affecting the accuracy of ADC conversions ...
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... TYP POR 0.12ms TYP MRST Figure 44:. ADuC7024/ADuC7025 Internal Power-on-Reset operation TYPICAL SYSEM CONFIGURATION A typical ADuC7024/ADuC7025 configuration is shown in Figure 45. It summarizes some of the hardware considerations discussed in the previous paragraphs. 1.98V TYP Figure 45:. Typical System Configuration Rev. PrB | Page ADuC702x Series ...
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... ADuC702x Series DEVELOPMENT TOOLS An entry level, low cost development system is available for the ADuC702X family. This system consists of the following PC- based (Windows® compatible) hardware development tools: Hardware: - ADuC702x Evaluation board - Serial Port programming cable - JTAG emulator Software: - Integrated Development Environment, incorporating ...
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... BSC SQ V IEW MAX TYP 0 .05 MAX 0 .02 NOM BSC REF COMPLIANT TO JEDEC STANDARDS MO -VMMD Rev Page ADuC702x Series 0.60 MAX PIN 1 INDICATOR 4.25 EXPOSED 4.10 SQ PAD 3.95 (BOTTOM VIEW) 21 ...
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... ADuC702x Series 0.024 ± 0.006 (0.60 ± 0.15) Figure 47. 64-Lead LQF Package [LQFP] (S-64)—Dimensions shown in millimetres 0.030 (0.75) 0.020 (0.50) 0.006 (0.15) 0.002 (0.05) Figure 2. 80-Lead LQF Package [LQFP] (S-80)—Dimensions shown in millimetres 0.063 (1.60) MAX 0.47(12.0) 0.006(0.15) BSC 0.002(0.05) 0.39(10.0) BSC TYP SEATING PLANE TOP VIEW ...