LPC2361FBD100,551 NXP Semiconductors, LPC2361FBD100,551 Datasheet - Page 30

• Manufacturer Part Number: LPC2361FBD100,551
• Description: IC ARM7 MCU FLASH 64K 100LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2300r

Specifications of LPC2361FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 64KB (64K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, I²C, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 34K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC23
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 34 KB
• Interface Type: CAN/I2S/SPI/SSP/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 70
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 100LQFP
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4310 - EVAL BOARD LPC2158 W/LCDMCB2360UME - BOARD EVAL MCB2360 + ULINK-MEMCB2360U - BOARD EVAL MCB2360 + ULINK2568-4014 - BOARD EVAL FOR LPC236X ARM568-3999 - BOARD EVAL FOR LPC23 ARM MCU
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4525; 935286991551

NXP Semiconductors
LPC2361_62_4
Product data sheet
7.24.1 Reset
7.24.2 Brownout detection
7.24 System control
On the LPC2361/2362, I/O pads are powered by the 3.3 V (V
V
the CPU and most of the peripherals.
Depending on the LPC2361/2362 application, a design can use two power options to
manage power consumption.
The first option assumes that power consumption is not a concern and the design ties the
V
supply for both pads, the CPU, and peripherals. While this solution is simple, it does not
support powering down the I/O pad ring “on the fly” while keeping the CPU and
peripherals alive.
The second option uses two power supplies; a 3.3 V supply for the I/O pads (V
a dedicated 3.3 V supply for the CPU (V
converter powered independently from the I/O pad ring enables shutting down of the I/O
pad power supply “on the fly”, while the CPU and peripherals stay active.
The VBAT pin supplies power only to the RTC and the battery RAM. These two functions
require a minimum of power to operate, which can be supplied by an external battery.
When the CPU and the rest of chip functions are stopped and power removed, the RTC
can supply an alarm output that may be used by external hardware to restore chip power
and resume operation.
Reset has four sources on the LPC2361/2362: the RESET pin, the Watchdog reset,
power-on reset, and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt
trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains
a usable level, starts the Wake-up timer (see description in
timer”), causing reset to remain asserted until the external Reset is de-asserted, the
oscillator is running, a fixed number of clocks have passed, and the flash controller has
completed its initialization.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the Boot Block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
The LPC2361/2362 includes 2-stage monitoring of the voltage on the V
If this voltage falls below 2.95 V, the BOD asserts an interrupt signal to the Vectored
Interrupt Controller. This signal can be enabled for interrupt in the Interrupt Enable
Register in the VIC in order to cause a CPU interrupt; if not, software can monitor the
signal by reading a dedicated status register.
The second stage of low-voltage detection asserts Reset to inactivate the LPC2361/2362
when the voltage on the V
alteration of the flash as operation of the various elements of the chip would otherwise
become unreliable due to low voltage. The BOD circuit maintains this reset down below
1 V, at which point the power-on reset circuitry maintains the overall Reset.
DD(DCDC)(3V3)
DD(3V3)
and V
pin powers the on-chip DC-to-DC converter which in turn provides power to
DD(DCDC)(3V3)
Rev. 04 — 4 March 2010
DD(DCDC)(3V3)
pins together. This approach requires only one 3.3 V power
pins falls below 2.65 V. This Reset prevents
DD(DCDC)(3V3)
). Having the on-chip DC-to-DC
Single-chip 16-bit/32-bit MCU
Section 7.23.3 “Wake-up
DD(3V3)
LPC2361/62
) pins, while the
DD(DCDC)(3V3)
© NXP B.V. 2010. All rights reserved.
DD(3V3)
30 of 57
) and
pins.