LPC2361FBD100,551 NXP Semiconductors, LPC2361FBD100,551 Datasheet - Page 19

IC ARM7 MCU FLASH 64K 100LQFP

LPC2361FBD100,551

Manufacturer Part Number
LPC2361FBD100,551
Description
IC ARM7 MCU FLASH 64K 100LQFP
Manufacturer
NXP Semiconductors
Series
LPC2300r
Datasheet

Specifications of LPC2361FBD100,551

Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
100-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, I²C, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
70
Ram Size
34K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC23
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
34 KB
Interface Type
CAN/I2S/SPI/SSP/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
70
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
6-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
100LQFP
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-4310 - EVAL BOARD LPC2158 W/LCDMCB2360UME - BOARD EVAL MCB2360 + ULINK-MEMCB2360U - BOARD EVAL MCB2360 + ULINK2568-4014 - BOARD EVAL FOR LPC236X ARM568-3999 - BOARD EVAL FOR LPC23 ARM MCU
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4525
935286991551

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LPC2361FBD100,551
Quantity:
9 999
Part Number:
LPC2361FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
LPC2361_62_4
Product data sheet
7.10.1.1 Features
7.10.1 USB device controller
7.10 USB interface
The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a
host and one or more (up to 127) peripherals. The Host Controller allocates the USB
bandwidth to attached devices through a token-based protocol. The bus supports hot
plugging and dynamic configuration of the devices. All transactions are initiated by the
Host Controller.
The LPC2361/2362 USB interface includes a device, Host, and OTG Controller. Details
on typical USB interfacing solutions can be found in
The device controller enables 12 Mbit/s data exchange with a USB Host Controller. It
consists of a register interface, serial interface engine, endpoint buffer memory, and a
DMA controller. The serial interface engine decodes the USB data stream and writes data
to the appropriate endpoint buffer. The status of a completed USB transfer or error
condition is indicated via status registers. An interrupt is also generated if enabled. When
enabled, the DMA controller transfers data between the endpoint buffer and the USB
RAM.
– Receive filtering.
– Multicast and broadcast frame support for both transmit and receive.
– Optional automatic Frame Check Sequence (FCS) insertion with Circular
– Selectable automatic transmit frame padding.
– Over-length frame support for both transmit and receive allows any length frames.
– Promiscuous receive mode.
– Automatic collision back-off and frame retransmission.
– Includes power management by clock switching.
– Wake-on-LAN power management support allows system wake-up: using the
Physical interface:
– Attachment of external PHY chip through standard RMII interface.
– PHY register access is available via the MIIM interface.
Fully compliant with USB 2.0 specification (full speed).
Supports 32 physical (16 logical) endpoints with a 4 kB endpoint buffer RAM.
Supports Control, Bulk, Interrupt and Isochronous endpoints.
Scalable realization of endpoints at run time.
Endpoint Maximum packet size selection (up to USB maximum specification) by
software at run time.
Supports SoftConnect and GoodLink features.
While the USB is in the Suspend mode, the LPC2361/2362 can enter one of the
reduced power modes and wake up on USB activity.
Redundancy Check (CRC) for transmit.
receive filters or a magic frame detection filter.
Rev. 04 — 4 March 2010
Section
Single-chip 16-bit/32-bit MCU
13.1.
LPC2361/62
© NXP B.V. 2010. All rights reserved.
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