LPC2361FBD100,551 NXP Semiconductors, LPC2361FBD100,551 Datasheet
LPC2361FBD100,551
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LPC2361/2362 Single-chip 16-bit/32-bit MCU 128 kB flash with ISP/IAP, Ethernet, USB 2.0 device/host/OTG, CAN, and 10-bit ADC/DAC Rev. 04 — 4 March 2010 1. General description The LPC2361/2362 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU with real-time ...
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... NXP Semiconductors Serial interfaces: Ethernet MAC with associated DMA controller (LPC2362 only). These functions reside on an independent AHB. USB 2.0 device/host/OTG with on-chip PHY and associated DMA controller. Four UARTs with fractional baud rate generation, one with modem control I/O, one with IrDA support, all with FIFO ...
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... NXP Semiconductors On-chip PLL allows CPU operation up to the maximum CPU rate without the need for a high frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the RTC oscillator. Versatile pin function selections allow more possibilities for using on-chip peripheral functions ...
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... NXP Semiconductors 5. Block diagram LPC2361/62 P0, P1, P2, P3, P4 HIGH-SPEED GPI/O 70 PINS TOTAL ETHERNET RMII(8) MAC WITH (1) DMA EINT3 to EINT0 EXTERNAL INTERRUPTS P0 × CAP0/CAP1/ CAPTURE/COMPARE CAP2/CAP3 TIMER0/TIMER1/ 4 × MAT2, TIMER2/TIMER3 2 × MAT0/MAT1/ MAT3 6 × PWM1 2 × PCAP1 LEGACY GPI/O P0 PINS TOTAL 6 × AD0 ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. 6.2 Pin description Table 3. Pin description Symbol Pin Type P0[0] to P0[31] I/O [1] P0[0]/RD1/TXD3/ 46 I/O SDA1 I O I/O [1] P0[1]/TD1/RXD3/ 47 I/O SCL1 O I I/O [1] P0[2]/TXD0 98 I/O O [1] P0[3]/RXD0 99 I/O I [1] P0[4]/I2SRX_CLK/ ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [1] P0[5]/I2SRX_WS/ 80 I/O TD2/CAP2[1] I [1] P0[6]/I2SRX_SDA/ 79 I/O SSEL1/MAT2[0] I/O I/O O [1] P0[7]/I2STX_CLK/ 78 I/O SCK1/MAT2[1] I/O I/O O [1] P0[8]/I2STX_WS/ 77 I/O MISO1/MAT2[2] I/O I/O O [1] P0[9]/I2STX_SDA/ 76 I/O MOSI1/MAT2[3] I/O I/O ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [1] P0[17]/CTS1/ 61 I/O MISO0/MISO I I/O I/O [1] P0[18]/DCD1/ 60 I/O MOSI0/MOSI I I/O I/O [1] P0[19]/DSR1/SDA1 59 I/O I I/O [1] P0[20]/DTR1/SCL1 58 I/O O I/O [1] P0[21]/RI1/RD1 57 I [1] P0[22]/RTS1/TD1 56 I [2] P0[23]/AD0[0]/ 9 I/O I2SRX_CLK/ I CAP3[0] I/O ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [4] P0[28]/SCL0 24 I/O I/O [5] P0[29]/USB_D+ 29 I/O I/O [5] P0[30]/USB_D− 30 I/O I/O P1[0] to P1[31] I/O [1] P1[0]/ENET_TXD0 95 I/O O [1] P1[1]/ENET_TXD1 94 I/O O [1] P1[4]/ENET_TX_EN 93 I/O O [1] P1[8]/ENET_CRS 92 I/O I [1] ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [1] P1[20]/ 34 I/O USB_TX_DP1/ O PWM1[2]/SCK0 O I/O [1] P1[21]/ 35 I/O USB_TX_DM1/ O PWM1[3]/SSEL0 O I/O [1] P1[22]/ 36 I/O USB_RCV1/ I USB_PWRD1/ I MAT1[0] O [1] P1[23]/ 37 I/O USB_RX_DP1/ I PWM1[4]/MISO0 O I/O [1] P1[24]/ 38 I/O USB_RX_DM1/ I PWM1[5]/MOSI0 O I/O [1] P1[25]/ 39 I/O ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [2] P1[30]/V /AD0[4] 21 I/O BUS I I [2] P1[31]/SCK1/AD0[5] 20 I/O I/O I P2[0] to P2[31] I/O [1] P2[0]/PWM1[1]/ 75 I/O TXD1/TRACECLK [1] P2[1]/PWM1[2]/ 74 I/O RXD1/PIPESTAT0 [1] P2[2]/PWM1[3]/ 73 I/O CTS1/PIPESTAT1 [1] P2[3]/PWM1[4]/ 70 I/O DCD1/PIPESTAT2 [1] P2[4]/PWM1[5]/ 69 I/O DSR1/TRACESYNC ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [1] P2[7]/RD2/RTS1/ 66 I/O TRACEPKT2 [1] P2[8]/TD2/TXD2/ 65 I/O TRACEPKT3 [1] P2[9]/ 64 I/O USB_CONNECT/ O RXD2/EXTIN0 I I [6] P2[10]/EINT0 53 I/O I [6] P2[11]/EINT1/ 52 I/O I2STX_CLK I I/O [6] P2[12]/EINT2/ 51 I/O I2STX_WS I I/O [6] P2[13]/EINT3/ 50 I/O I2STX_SDA I I/O ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [1] P4[28]/MAT2[0]/ 82 I/O TXD3 O O [1] P4[29]/MAT2[1]/ 85 I/O RXD3 O I [1] TDO 1 O [1] TDI 2 I [1] TMS 3 I [1] TRST 4 I [1] TCK 5 I [1] RTCK 100 I/O RSTOUT 14 O [7] RESET 17 I [8][9] XTAL1 22 I [8][9] XTAL2 ...
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... NXP Semiconductors [ tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output, digital section of the pad is disabled. [4] Open-drain 5 V tolerant digital I/O pad, compatible with I output functionality. When power is switched off, this pin connected to the I Open-drain configuration applies to all functions on this pin ...
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... NXP Semiconductors decode mechanism are much simpler than those of microprogrammed complex instruction set computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously ...
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... NXP Semiconductors In addition, the CPU interrupt vectors may be remapped to allow them to reside in either flash memory (default), boot ROM, or SRAM (see 3.75 GB Fig 3. 7.5 Interrupt controller The ARM processor core has two interrupt inputs called Interrupt Request (IRQ) and Fast Interrupt Request (FIQ). The VIC takes 32 interrupt request inputs which can be programmed as FIQ or vectored IRQ types ...
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... NXP Semiconductors FIQs have the highest priority. If more than one request is assigned to FIQ, the VIC ORs the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classified as FIQ, because then the FIQ service routine can simply start dealing with that device ...
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... NXP Semiconductors • Single DMA and burst DMA request signals. Each peripheral connected to the GPDMA can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the GPDMA. • Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers. • ...
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... NXP Semiconductors Additionally, any pin on PORT0 and PORT2 (total of 42 pins) providing a digital function can be programmed to generate an interrupt on a rising edge, a falling edge, or both. The edge detection is asynchronous may operate when clocks are not present such as during Power-down mode. Each enabled interrupt can be used to wake up the chip from Power-down mode ...
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... NXP Semiconductors – Receive filtering. – Multicast and broadcast frame support for both transmit and receive. – Optional automatic Frame Check Sequence (FCS) insertion with Circular Redundancy Check (CRC) for transmit. – Selectable automatic transmit frame padding. – Over-length frame support for both transmit and receive allows any length frames. ...
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... NXP Semiconductors • Supports DMA transfers with the DMA RAM all non-control endpoints. • Allows dynamic switching between CPU-controlled and DMA modes. • Double buffer implementation for Bulk and Isochronous endpoints. 7.10.2 USB host controller The host controller enables full- and low-speed data exchange with USB devices attached to the bus ...
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... NXP Semiconductors 7.11.1 Features • Two CAN controllers and buses. • Data rates to 1 Mbit/s on each bus. • 32-bit register and RAM access. • Compatible with CAN specification 2.0B, ISO 11898-1. • Global Acceptance Filter recognizes 11-bit and 29-bit receive identifiers for all CAN buses. • ...
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... NXP Semiconductors 7.14.1 Features • Receive and Transmit FIFOs. • Register locations conform to 16C550 industry standard. • Receiver FIFO trigger points and 14 B. • Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. ...
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... NXP Semiconductors 2 7.17 I C-bus serial I/O controllers The LPC2361/2362 each contain three I 2 The I C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line (SCL), and a serial data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver transmitter with the capability to both receive and send information (such as memory) ...
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... NXP Semiconductors • Configurable word select period in master mode (separately for I • Two 8-word FIFO data buffers are provided, one for transmit and one for receive. • Generates interrupt requests when buffer levels cross a programmable boundary. • Two DMA requests, controlled by programmable buffer levels. These are connected to the GPDMA block. • ...
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... NXP Semiconductors controlled PWM outputs require only one match register each, since the repetition rate is the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs. ...
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... NXP Semiconductors • Debug mode. • Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. • Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. • Flag to indicate watchdog reset. • Programmable 32-bit timer with internal prescaler. • Selectable time period from (T multiples of T • ...
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... NXP Semiconductors Following reset, the LPC2361/2362 will operate from the Internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency. 7.23.1.1 Internal RC oscillator The IRC may be used as the clock source for the WDT, and/or as the clock that drives the PLL and subsequently the CPU ...
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... NXP Semiconductors 7.23.3 Wake-up timer The LPC2361/2362 begins operation at power-up and when awakened from Power-down and Deep power-down modes by using the 4 MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source ...
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... NXP Semiconductors 32 kHz RTC oscillator is not stopped because the RTC interrupts may be used as the wake-up source. The PLL is automatically turned off and disconnected. The CCLK and USB clock dividers automatically get reset to zero. The Sleep mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks ...
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... NXP Semiconductors On the LPC2361/2362, I/O pads are powered by the 3 DD(DCDC)(3V3) the CPU and most of the peripherals. Depending on the LPC2361/2362 application, a design can use two power options to manage power consumption. The first option assumes that power consumption is not a concern and the design ties the ...
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... NXP Semiconductors Both the 2.95 V and 2.65 V thresholds include some hysteresis. In normal operation, this hysteresis allows the 2.95 V detection to reliably interrupt regularly executed event loop to sense the condition. 7.24.3 Code security (Code Read Protection - CRP) This feature of the LPC2361/2362 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the JTAG and ISP can be restricted ...
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... NXP Semiconductors 7.24.6 Memory mapping control The memory mapping control alters the mapping of the interrupt vectors that appear at the beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the Boot ROM or the SRAM. This allows code running in different memory spaces to have control of the interrupts ...
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... NXP Semiconductors Since trace information is compressed the software debugger requires a static image of the code being executed. Self-modifying code can not be traced because of this restriction. 7.25.3 RealMonitor RealMonitor is a configurable software module, developed by ARM Inc., which enables real-time debug lightweight debug monitor that runs in the background while users debug their foreground application ...
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... NXP Semiconductors 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (3.3 V) DD(3V3) V DC-to-DC converter supply voltage DD(DCDC)(3V3) (3 analog 3.3 V pad supply voltage DDA V input voltage on pin VBAT i(VBAT) V input voltage on pin VREF ...
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... NXP Semiconductors 9. Static characteristics Table 5. Static characteristics − ° ° +85 C for commercial applications, unless otherwise specified. amb Symbol Parameter V supply voltage (3.3 V) DD(3V3) V DC-to-DC converter DD(DCDC)(3V3) supply voltage (3 analog 3.3 V pad supply DDA voltage V input voltage on pin i(VBAT) VBAT ...
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... NXP Semiconductors Table 5. Static characteristics − ° ° +85 C for commercial applications, unless otherwise specified. amb Symbol Parameter I I/O latch-up current latch V input voltage I V output voltage O V HIGH-level input IH voltage V LOW-level input voltage IL V hysteresis voltage hys V HIGH-level output OH voltage ...
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... NXP Semiconductors Table 5. Static characteristics − ° ° +85 C for commercial applications, unless otherwise specified. amb Symbol Parameter USB pins I OFF-state output OZ current V bus supply voltage BUS V differential input DI sensitivity voltage V differential common CM mode voltage range V single-ended receiver th(rs)se switching threshold ...
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... NXP Semiconductors 9.1 Power-down mode I DD(IO) (μA) Fig 4. I (μA) Fig 5. LPC2361_62_4 Product data sheet −2 −4 −40 − 3 i(VBAT) DD(DCDC)(3V3) amb I/O maximum supply current I 40 BAT 3.3 V i(VBAT 3.0 V i(VBAT −40 − 3 DD(3V3) DD(DCDC)(3V3) RTC battery maximum supply current I mode Rev. 04 — ...
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... NXP Semiconductors I DD(DCDC)pd(3v3) Fig 6. 9.2 Deep power-down mode I DD(IO) (μA) Fig 7. LPC2361_62_4 Product data sheet 800 (μA) 600 400 V = 3.3 V DD(DCDC)(3V3) 200 V = 3.0 V DD(DCDC)(3V3) 0 −40 − ° 3 DD(3V3) i(VBAT) amb Total DC-to-DC converter supply current I in Power-down mode 300 ...
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... NXP Semiconductors I (μA) Fig 8. I DD(DCDC)dpd(3v3) Fig 9. LPC2361_62_4 Product data sheet 40 BAT 3.3 V i(VBAT 3.0 V i(VBAT −40 − 3 DD(3V3) DD(DCDC)(3V3) RTC battery maximum supply current I power-down mode 100 (μ 3.3 V DD(DCDC)(3V3 3.0 V DD(DCDC)(3V3 −40 − ° 3 DD(3V3) i(VBAT) ...
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... NXP Semiconductors 10. Dynamic characteristics Table 6. Dynamic characteristics − ° ° +85 C for commercial applications; V amb Symbol Parameter ARM processor clock frequency f operating frequency oper External clock f oscillator frequency osc T clock cycle time cy(clk) t clock HIGH time CHCX t clock LOW time CLCX ...
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... NXP Semiconductors Table 8. Dynamic characteristics of flash − ° ° +85 C for commercial applications, unless otherwise specified; V amb measured with respect to ground. Symbol Parameter N endurance endu t retention time ret [1] Number of program/erase cycles. [2] t specified for < 1 ppm. ret LPC2361_62_4 Product data sheet ...
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... NXP Semiconductors 10.1 Timing Fig 10. External clock timing (with an amplitude of at least V T PERIOD differential data lines Fig 11. Differential data-to-EOP transition skew and EOP width shifting edges SCK MOSI MISO Fig 12. MISO line set-up time in SSP Master mode LPC2361_62_4 Product data sheet ...
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... NXP Semiconductors 11. ADC electrical characteristics Table 9. ADC characteristics − 2 3 DDA amb Symbol Parameter V analog input voltage IA C analog input capacitance ia E differential linearity error D E integral non-linearity L(adj) E offset error O E gain error G E absolute error T R voltage source interface ...
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... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. Fig 13. ADC characteristics LPC2361_62_4 Product data sheet ...
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... NXP Semiconductors AD0[y] Fig 14. Suggested ADC interface - LPC2361/2362 AD0[y] pin LPC2361_62_4 Product data sheet LPC23XX 20 kΩ SAMPLE Rev. 04 — 4 March 2010 LPC2361/62 Single-chip 16-bit/32-bit MCU R vsi AD0[y] V EXT 002aac610 © NXP B.V. 2010. All rights reserved ...
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... NXP Semiconductors 12. DAC electrical characteristics Table 10. DAC electrical characteristics − 2 3 DDA amb Symbol Parameter E differential linearity error D E integral non-linearity L(adj) E offset error O E gain error G C load capacitance L R load resistance L 13. Application information 13.1 Suggested USB interface solutions LPC23XX Fig 15 ...
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... NXP Semiconductors LPC23XX Fig 16. LPC2361/2362 USB interface on a bus-powered device RSTOUT LPC2361/62 USB_SCL USB_SDA EINTn USB_D+ USB_D− Fig 17. LPC2361/2362 USB OTG port configuration LPC2361_62_4 Product data sheet V DD(3V3 USB_UP_LED 1.5 kΩ V BUS Ω USB_D Ω USB_D− RESET_N ADR/PSW OE_N/INT_N ...
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... NXP Semiconductors USB_UP_LED USB_D+ USB_D− LPC2361/62 USB_PWRD USB_OVRCR USB_PPWR Fig 18. LPC2361/2362 USB host port configuration USB_UP_LED USB_CONNECT LPC2361/62 USB_D+ USB_D− V BUS Fig 19. LPC2361/2362 USB device port configuration 13.2 XTAL1 input The input voltage to the on-chip oscillators is limited to 1 the oscillator is driven by a ...
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... NXP Semiconductors Fig 20. Slave mode operation of the on-chip oscillator 13.3 XTAL and RTC Printed Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors C case of third overtone crystal usage, have a common ground plane ...
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... NXP Semiconductors 14. Package outline LQFP100: plastic low profile quad flat package; 100 leads; body 1 pin 1 index 100 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 mm 1.6 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 15. Abbreviations Table 11. Acronym ADC AHB AMBA APB BOD CAN DAC DCC DMA DSP EOP ETM GP GPIO IrDA JTAG MCU MII MIIM OHCI OTG PHY PLL PWM RMII SE0 SPI SSI SSP TTL UART USB LPC2361_62_4 Product data sheet Abbreviations ...
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... NXP Semiconductors 16. Revision history Table 12. Revision history Document ID LPC2361_62_4 Modifications: LPC2361_62_3 Modifications: LPC2361_62_2 Modifications: LPC2361_62_1 LPC2361_62_4 Product data sheet Release date Data sheet status 20100304 Product data sheet • Table 3 “Pin description”: Added table note for XTAL1 and XTAL2 pins. ...
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... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . 13 7.1 Architectural overview . . . . . . . . . . . . . . . . . . 13 7.2 On-chip flash programming memory . . . . . . . 14 7.3 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 14 7.4 Memory map ...
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... NXP Semiconductors 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 51 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 52 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 53 17 Legal information 17.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 54 17.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 17.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 17.4 Trademarks Contact information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 LPC2361/62 Single-chip 16-bit/32-bit MCU Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. ...