AT90USB646-MU Atmel, AT90USB646-MU Datasheet - Page 36

• Manufacturer Part Number: AT90USB646-MU
• Description: IC AVR MCU 64K 64QFN
• Manufacturer: Atmel
• Series: AVR® 90USBr

Specifications of AT90USB646-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 48
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Processor Series: 90USB
• Core: AVR
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, TWI, USART, USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 4
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Cpu Family: AT90
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 20MHz
• Total Internal Ram Size: 4KB
• # I/os (max): 48
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: QFN EP
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATSTK525 - KIT STARTER FOR AT90USBAT90USBKEY2 - KIT DEMO FOR AT90USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AT90USB646-16MU; AT90USB646-16MU

5.5.8
36
AT90USB64/128
Using all Locations of External Memory Smaller than 64 KB
so even if the XMEM interface is disabled, the bus keepers are still activated as long as XMBK is
one.
• Bit 6..3 – Res: Reserved Bits
These bits are reserved and will always read as zero. When writing to this address location,
write these bits to zero for compatibility with future devices.
• Bit 2..0 – XMM2, XMM1, XMM0: External Memory High Mask
When the External Memory is enabled, all Port C pins are default used for the high address byte.
If the full 60KB address space is not required to access the External Memory, some, or all, Port
C pins can be released for normal Port Pin function as described in
“Using all 64KB Locations of External Memory” on page
access all 64KB locations of the External Memory.
Table 5-6.
Since the external memory is mapped after the internal memory as shown in
external memory is not addressed when addressing the first 8,448/4,352 bytes (128/64Kbytes
version) of data space. It may appear that the first 8,448/4,352 bytes of the external memory are
inaccessible (external memory addresses 0x0000 to 0x10FF or 0x0000 to 0x20FF). However,
when connecting an external memory smaller than 64 KB, for example 32 KB, these locations
are easily accessed simply by addressing from address 0x8000 to 0xA1FF. Since the External
Memory Address bit A15 is not connected to the external memory, addresses 0x8000 to 0xA1FF
will appear as addresses 0x0000 to 0x21FF for the external memory. Addressing above address
0xA1FF is not recommended, since this will address an external memory location that is already
accessed by another (lower) address. To the Application software, the external 32 KB memory
will appear as one linear 32 KB address space from 0x2200 to 0xA1FF. This is illustrated in
ure
XMM2
0
0
0
0
1
1
1
1
5-10.
XMM1
0
0
1
1
0
0
1
1
Port C Pins Released as Normal Port Pins when the External Memory is Enabled
XMM0
0
1
0
1
0
1
0
1
# Bits for External Memory Address
8 (Full 56KB space)
7
6
5
4
3
2
No Address high bits
37, it is possible to use the XMMn bits to
Released Port Pins
None
PC7
PC7 - PC6
PC7 - PC5
PC7 - PC4
PC7 - PC3
PC7 - PC2
Full Port C
Table
5-6. As described in
Figure
7593K–AVR–11/09
5-4, the
Fig-