AT90USB646-MU Atmel, AT90USB646-MU Datasheet - Page 178

• Manufacturer Part Number: AT90USB646-MU
• Description: IC AVR MCU 64K 64QFN
• Manufacturer: Atmel
• Series: AVR® 90USBr

Specifications of AT90USB646-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 48
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Processor Series: 90USB
• Core: AVR
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, TWI, USART, USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 4
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Cpu Family: AT90
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 20MHz
• Total Internal Ram Size: 4KB
• # I/os (max): 48
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: QFN EP
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATSTK525 - KIT STARTER FOR AT90USBAT90USBKEY2 - KIT DEMO FOR AT90USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AT90USB646-16MU; AT90USB646-16MU

17.1.4
178
AT90USB64/128
SPI Status Register – SPSR
and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas-
ter mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low
when idle. Refer to
marized below:
Table 17-2.
• Bit 2 – CPHA: Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or
trailing (last) edge of SCK. Refer to
functionality is summarized below:
Table 17-3.
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have
no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency f
shown in the following table:
Table 17-4.
• Bit 7 – SPIF: SPI Interrupt Flag
Bit
Read/Write
Initial Value
SPI2X
0
0
0
0
1
1
1
1
CPOL
CPHA
0
1
0
1
7
SPIF
R
0
CPOL Functionality
CPHA Functionality
Relationship Between SCK and the Oscillator Frequency
Figure 17-3
6
WCOL
R
0
SPR1
0
0
1
1
0
0
1
1
5
–
R
0
and
Leading Edge
Leading Edge
Figure 17-4
Figure 17-3
4
–
R
0
Sample
Falling
Rising
Setup
SPR0
0
1
0
1
0
1
0
1
3
–
R
0
for an example. The CPOL functionality is sum-
and
SCK Frequency
f
f
f
f
f
f
f
f
osc
osc
osc
osc
osc
osc
osc
osc
2
–
R
0
Figure 17-4
/
/
/
/
/
/
/
/
4
16
64
128
2
8
32
64
1
–
R
0
Trailing Edge
Trailing Edge
for an example. The CPOL
Sample
Falling
Rising
Setup
0
SPI2X
R/W
0
SPSR
7593K–AVR–11/09
osc
is