AT90USB646-MU Atmel, AT90USB646-MU Datasheet - Page 201

IC AVR MCU 64K 64QFN

AT90USB646-MU

Manufacturer Part Number
AT90USB646-MU
Description
IC AVR MCU 64K 64QFN
Manufacturer
Atmel
Series
AVR® 90USBr
Datasheet

Specifications of AT90USB646-MU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART, USB, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
Processor Series
90USB
Core
AVR
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
SPI, TWI, USART, USB
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
48
Number Of Timers
4
Operating Supply Voltage
5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Cpu Family
AT90
Device Core
AVR
Device Core Size
8b
Frequency (max)
20MHz
Total Internal Ram Size
4KB
# I/os (max)
48
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
QFN EP
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATSTK525 - KIT STARTER FOR AT90USBAT90USBKEY2 - KIT DEMO FOR AT90USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
AT90USB646-16MU
AT90USB646-16MU

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT90USB646-MU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
18.9.4
7593K–AVR–11/09
USART Control and Status Register n C – UCSRnC
zero) will not become effective until ongoing and pending transmissions are completed, i.e.,
when the Transmit Shift Register and Transmit Buffer Register do not contain data to be trans-
mitted. When disabled, the Transmitter will no longer override the TxDn port.
• Bit 2 – UCSZn2: Character Size n
The UCSZn2 bits combined with the UCSZn1:0 bit in UCSRnC sets the number of data bits
(Character SiZe) in a frame the Receiver and Transmitter use.
• Bit 1 – RXB8n: Receive Data Bit 8 n
RXB8n is the ninth data bit of the received character when operating with serial frames with nine
data bits. Must be read before reading the low bits from UDRn.
• Bit 0 – TXB8n: Transmit Data Bit 8 n
TXB8n is the ninth data bit in the character to be transmitted when operating with serial frames
with nine data bits. Must be written before writing the low bits to UDRn.
• Bits 7:6 – UMSELn1:0 USART Mode Select
These bits select the mode of operation of the USARTn as shown in
Table 18-4.
Note:
• Bits 5:4 – UPMn1:0: Parity Mode
These bits enable and set type of parity generation and check. If enabled, the Transmitter will
automatically generate and send the parity of the transmitted data bits within each frame. The
Receiver will generate a parity value for the incoming data and compare it to the UPMn setting.
If a mismatch is detected, the UPEn Flag in UCSRnA will be set.
Table 18-5.
Bit
Read/Write
Initial Value
UMSELn1
UPMn1
1. See
0
0
1
1
0
0
1
1
operation
7
UMSELn1
R/W
0
UMSELn Bits Settings
UPMn Bits Settings
“USART in SPI Mode” on page 206
6
UMSELn0
R/W
0
UMSELn0
UPMn0
0
1
0
1
0
1
0
1
UPMn1
R/W
5
0
Parity Mode
Disabled
Reserved
Enabled, Even Parity
Enabled, Odd Parity
UPMn0
R/W
4
0
Mode
Asynchronous USART
Synchronous USART
(Reserved)
Master SPI (MSPIM)
3
USBSn
R/W
0
for full description of the Master SPI Mode (MSPIM)
2
UCSZn1
R/W
1
(1)
1
UCSZn0
R/W
1
AT90USB64/128
Table
0
UCPOLn
R/W
0
18-4..
UCSRnC
201

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