ATMEGA169V-1MC Atmel, ATMEGA169V-1MC Datasheet - Page 92

• Manufacturer Part Number: ATMEGA169V-1MC
• Description: IC MCU AVR 16K 1.8V 1MHZ 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA169V-1MC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 1MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-MLF®, 64-QFN
• For Use With: ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Output Compare Register A –
OCR0A
Timer/Counter 0 Interrupt
Mask Register – TIMSK0
Timer/Counter 0 Interrupt Flag
Register – TIFR0
92
ATmega169V/L
The Output Compare Register A contains an 8-bit value that is continuously compared
with the counter value (TCNT0). A match can be used to generate an Output Compare
interrupt, or to generate a waveform output on the OC0A pin.
• Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one, and the I-bit in the Status Register is set (one),
the Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt
is executed if a compare match in Timer/Counter0 occurs, i.e., when the OCF0A bit is
set in the Timer/Counter 0 Interrupt Flag Register – TIFR0.
• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if
a n o verflo w in Timer/Coun ter0 occurs, i.e ., when the TO V0 b it is set in th e
Timer/Counter 0 Interrupt Flag Register – TIFR0.
• Bit 1 – OCF0A: Output Compare Flag 0 A
The OCF0A bit is set (one) when a compare match occurs between the Timer/Counter0
and the data in OCR0A – Output Compare Register0. OCF0A is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, OCF0A is
cleared b y w riting a logic o ne to the flag . Wh en the I-bit in SREG , OCIE0A
(Timer/Counter0 Compare match Interrupt Enable), and OCF0A are set (one), the
Timer/Counter0 Compare match Interrupt is executed.
• Bit 0 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared
by hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0
( Tim er /Co u nte r0 O v er flo w In ter ru p t En ab le ), a n d TO V 0 ar e se t (o n e) , th e
Timer/Counter0 Overflow interrupt is executed. In phase correct PWM mode, this bit is
set when Timer/Counter0 changes counting direction at 0x00.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
R/W
R
R
7
0
7
–
0
7
–
0
R/W
R
R
6
0
6
–
0
6
–
0
R/W
5
0
5
–
R
0
5
–
R
0
R/W
R
R
4
0
4
–
0
4
–
0
OCR0A[7:0]
R/W
R
R
3
0
3
–
0
3
–
0
R/W
R
R
2
0
2
–
0
2
–
0
OCIE0A
OCF0A
R/W
R/W
R/W
1
0
1
0
1
0
TOIE0
TOV0
R/W
R/W
R/W
0
0
0
0
0
0
2514H–AVR–05/03
TIMSK0
OCR0
TIFR0