ATMEGA169V-1MC Atmel, ATMEGA169V-1MC Datasheet - Page 43

• Manufacturer Part Number: ATMEGA169V-1MC
• Description: IC MCU AVR 16K 1.8V 1MHZ 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA169V-1MC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 1MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-MLF®, 64-QFN
• For Use With: ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Watchdog Timer Control
Register – WDTCR
2514H–AVR–05/03
• Bits 7..5 – Res: Reserved Bits
These bits are reserved bits in the ATmega169 and will always read as zero.
• Bit 4 – WDCE: Watchdog Change Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog
will not be disabled. Once written to one, hardware will clear this bit after four clock
cycles. Refer to the description of the WDE bit for a Watchdog disable procedure. This
bit must also be set when changing the prescaler bits. See “Timed Sequences for
Changing the Configuration of the Watchdog Timer” on page 44.
• Bit 3 – WDE: Watchdog Enable
When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is
written to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared
if the WDCE bit has logic level one. To disable an enabled Watchdog Timer, the follow-
ing procedure must be followed:
1. In the same operation, write a logic one to WDCE and WDE. A logic one must be
2. Within the next four clock cycles, write a logic 0 to WDE. This disables the
In safety level 2, it is not possible to disable the Watchdog Timer, even with the algo-
rithm described above. See “Timed Sequences for Changing the Configuration of the
Watchdog Timer” on page 44.
• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0
The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the
Watchdog Timer is enabled. The different prescaling values and their corresponding
Timeout Periods are shown in Table 21.
Table 21. Watchdog Timer Prescale Select
Bit
Read/Write
Initial Value
WDP2
0
0
0
0
1
1
1
1
written to WDE even though it is set to one before the disable operation starts.
Watchdog.
WDP1
0
0
1
1
0
0
1
1
R
7
–
0
WDP0
0
1
0
1
0
1
0
1
R
6
–
0
Oscillator Cycles
Number of WDT
1,024K cycles
2,048K cycles
128K cycles
256K cycles
512K cycles
16K cycles
32K cycles
64K cycles
5
–
R
0
WDCE
R/W
4
0
WDE
R/W
3
0
Typical Time-out
at V
17.1 ms
34.3 ms
68.5 ms
0.14 s
0.27 s
0.55 s
WDP2
CC
1.1 s
2.2 s
R/W
2
0
= 3.0V
ATmega169V/L
WDP1
R/W
1
0
Typical Time-out
at V
WDP0
R/W
0
0
16.3 ms
32.5 ms
65 ms
0.13 s
0.26 s
0.52 s
CC
1.0 s
2.1 s
= 5.0V
WDTCR
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