ATMEGA169V-1MC Atmel, ATMEGA169V-1MC Datasheet - Page 81

• Manufacturer Part Number: ATMEGA169V-1MC
• Description: IC MCU AVR 16K 1.8V 1MHZ 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA169V-1MC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 1MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-MLF®, 64-QFN
• For Use With: ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Output Compare Unit
2514H–AVR–05/03
Depending of the mode of operation used, the counter is cleared, incremented, or dec-
remented at each timer clock (clk
clock source, selected by the Clock Select bits (CS02:0). When no clock source is
selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed
by the CPU, regardless of whether clk
priority over) all counter clear or count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits
located in the Timer/Counter Control Register (TCCR0A). There are close connections
between how the counter behaves (counts) and how waveforms are generated on the
Output Compare output OC0A. For more details about advanced counting sequences
and waveform generation, see “Modes of Operation” on page 84.
The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation
selected by the WGM01:0 bits. TOV0 can be used for generating a CPU interrupt.
The 8-bit comparator continuously compares TCNT0 with the Output Compare Register
(OCR0A). Whenever TCNT0 equals OCR0A, the comparator signals a match. A match
will set the Output Compare Flag (OCF0A) at the next timer clock cycle. If enabled
(OCIE0A = 1 and Global Interrupt Flag in SREG is set), the Output Compare Flag gen-
erates an Output Compare interrupt. The OCF0A Flag is automatically cleared when the
interrupt is executed. Alternatively, the OCF0A Flag can be cleared by software by writ-
ing a logical one to its I/O bit location. The Waveform Generator uses the match signal
to generate an output according to operating mode set by the WGM01:0 bits and Com-
pare Output mode (COM0A1:0) bits. The max and bottom signals are used by the
Waveform Generator for handling the special cases of the extreme values in some
modes of operation (See “Modes of Operation” on page 84.).
Figure 28 shows a block diagram of the Output Compare unit.
Figure 28. Output Compare Unit, Block Diagram
bottom
FOCn
top
OCRnx
T0
Waveform Generator
WGMn1:0
=
). clk
(8-bit Comparator )
DATA BUS
T0
T0
is present or not. A CPU write overrides (has
can be generated from an external or internal
COMnX1:0
ATmega169V/L
TCNTn
OCFnx (Int.Req.)
OCnx
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