ATMEGA169V-1MC Atmel, ATMEGA169V-1MC Datasheet
ATMEGA169V-1MC
Specifications of ATMEGA169V-1MC
Related parts for ATMEGA169V-1MC
ATMEGA169V-1MC Summary of contents
Page 1
... I/O and Packages – 53 Programmable I/O Lines – 64-lead TQFP and 64-pad MLF • Operating Voltage: – 1.8 - 5.5V for ATmega169V – 2.7 - 5.5V for ATmega169L – 4.5 - 5.5V for ATmega169 • Temperature range: – -40°C to 85°C Industrial ® ...
Page 2
... Features (Continued) • Speed Grade: – MHz for ATmega169V – MHz for ATmega169L – MHz for ATmega169 • Ultra-Low Power Consumption – Active Mode: 1 MHz, 1.8V: 400µA 32 kHz, 1.8V: 20µA (including Oscillator) 32 kHz, 1.8V: 40µA (including Oscillator and LCD) – Power-down Mode: 0.5µ ...
Page 3
... STATUS REGISTER SPI DATA REGISTER DATA DIR. DATA REGISTER REG. PORTB PORTB PORTD PORTB DRIVERS PORTD DRIVERS PB0 - PB7 PD0 - PD7 ATmega169V/L PC0 - PC7 PORTC DRIVERS DATA DIR. REG. PORTC CALIB. OSC OSCILLATOR TIMING AND CONTROL LCD CONTROLLER/ DRIVER DATA DIR. ...
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... The ATmega169 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Cir- cuit Emulators, and Evaluation kits. ATmega169V/L 4 2514H–AVR–05/03 ...
Page 5
... Port F (PF7..PF0) Port F serves as the analog inputs to the A/D Converter. Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output 2514H–AVR–05/03 ATmega169V/L 5 ...
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... Be aware that not all C compiler vendors include bit defini- tions in the header files and interrupt handling compiler dependent. Please confirm with the C compiler documentation for more details. ATmega169V even if the ADC is not used. If the ADC is used, it should be con- CC through a low-pass filter ...
Page 7
... In a typical ALU operation, two operands are output from the Register File, 2514H–AVR–05/03 Program Flash Counter Program Memory Instruction Register Instruction Decoder Control Lines ATmega169V/L Data Bus 8-bit Status and Control Interrupt Unit General Purpose SPI Registrers Unit Watchdog ...
Page 8
... ALU operations are divided into three main categories – arithmetic, logical, and bit-func- tions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruc- tion Set” section for a detailed description. ATmega169V/L 8 2514H–AVR–05/03 ...
Page 9
... Set Description” for detailed information. • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 2514H–AVR–05/03 Bit Read/Write R/W R/W R/W Initial Value ATmega169V R/W R/W R/W R/W R ...
Page 10
... SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file. ATmega169V/L 10 One 8-bit output operand and one 8-bit result input Two 8-bit output operands and one 8-bit result input ...
Page 11
... ZH Z-register 7 0 R31 (0x1F) Bit SP15 SP14 SP13 SP7 SP6 SP5 Read/Write R/W R/W R/W R/W R/W R/W Initial Value ATmega169V R26 (0x1A R28 (0x1C R30 (0x1E SP12 SP11 SP10 SP9 SP8 SP4 SP3 SP2 SP1 SP0 R/W R/W R/W ...
Page 12
... RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 46 for more information. The Reset Vector can also be ATmega169V clk ...
Page 13
... EECR, EEWE ; restore SREG value (I-bit) out SREG, r16 C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1<<EEMWE); /* start EEPROM write */ EECR |= (1<<EEWE); SREG = cSREG; /* restore SREG value (I-bit) */ ATmega169V/L 13 ...
Page 14
... A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. ATmega169V/L 14 Assembly Code Example sei ...
Page 15
... LPM – Load Program Memory instruction description). Timing diagrams for instruction fetch and execution are presented in “Instruction Execu- tion Timing” on page 12. Figure 8. Program Memory Map 2514H–AVR–05/03 ATmega169V/L Program Memory 0x0000 Application Flash Section Boot Flash Section 0x1FFF ...
Page 16
... The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Regis- ters, and the 1,024 bytes of internal data SRAM in the ATmega169 are all accessible through all these addressing modes. The Register File is described in “General Purpose Register File” on page 10. Figure 9. Data Memory Map ATmega169V/L 16 Data Memory 0x0000 - 0x001F 32 Registers ...
Page 17
... When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. 2514H–AVR–05/03 T1 clk CPU Address Compute Address Data WR Data RD Memory Access Instruction is likely to rise or fall slowly on power-up/down. This CC ATmega169V/L cycles as described in Figure CPU T2 T3 Address valid Next Instruction 17 ...
Page 18
... When EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure. ATmega169V/L 18 Bit 15 ...
Page 19
... The calibrated Oscillator is used to time the EEPROM accesses. Table 1 lists the typical programming time for EEPROM access from the CPU. Table 1. EEPROM Programming Time 2514H–AVR–05/03 Symbol Number of Calibrated RC Oscillator Cycles EEPROM write (from CPU) ATmega169V/L Typ Programming Time 67 584 8 ...
Page 20
... The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM com- mand to finish. ATmega169V/L 20 Assembly Code Example EEPROM_write: ...
Page 21
... EEPROM_read(unsigned int uiAddress Wait for completion of previous write */ while(EECR & (1<<EEWE Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from Data Register */ return EEDR; } the EEPROM data can be corrupted because the supply volt- CC, ATmega169V/L 21 ...
Page 22
... SBI, CBI, SBIS, and SBIC instructions. General Purpose I/O Register 2 – GPIOR2 General Purpose I/O Register 1 – GPIOR1 General Purpose I/O Register 0 – GPIOR0 ATmega169V/L 22 reset Protection circuit can be used reset occurs while a write operation Bit 7 6 ...
Page 23
... Asynchronous General I/O LCD Controller Timer/Counter Modules clk I/O clk ASY Timer/Counter External Clock Oscillator ATmega169V/L CPU Core RAM clk AVR Clock CPU Control Unit clk FLASH Reset Logic Watchdog Timer Source clock Watchdog clock Clock ...
Page 24
... The default clock source setting is the Internal RC Oscillator with longest start-up time and an initial system clock prescaling of 8. This default setting ensures that all users can make their desired clock source setting using an In-System or Parallel programmer. ATmega169V/L 24 Device Clocking Option External Crystal/Ceramic Resonator ...
Page 25
... C2 C1 CKSEL3..1 Frequency Range (MHz) (1) 100 0.4 - 0.9 101 0.9 - 3.0 110 3.0 - 8.0 111 8 This option should not be used with crystals, only with ceramic resonators. ATmega169V/L XTAL2 XTAL1 GND Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF) – ...
Page 26
... The crystal should be connected as shown in Figure 12. When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 6 and CKSEL1..0 as shown in Table 7. Table 6. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection ATmega169V/L 26 Start-up Time from Power-down and CKSEL0 SUT1 ...
Page 27
... The device is shipped with this option selected. Start-up Time from Power- SUT1..0 down and Power-save ( The device is shipped with this option selected. ATmega169V/L Recommended Usage Stable frequency at start-up Stable frequency at start-up (1) Nominal Frequency 8.0 MHz Additional Delay from Reset (V = 5.0V) Recommended Usage CC 14CK BOD enabled 14CK + 4 ...
Page 28
... EEPROM and Flash access. If EEPROM or Flash is written, do not cali- brate to more than 10% above the nominal frequency. Otherwise, the EEPROM or Flash write may fail. Note that the Oscillator is intended for calibration to 8.0 MHz. Tuning to other values is not guaranteed, as indicated in Table 10. Table 10. Internal RC Oscillator Frequency Range. ATmega169V/L 28 Bit – ...
Page 29
... EXTERNAL CLOCK SIGNAL CKSEL3..0 Frequency Range 0000 MHz Start-up Time from Power- SUT1..0 down and Power-save ATmega169V/L XTAL2 XTAL1 GND Additional Delay from Reset (V = 5.0V) Recommended Usage CC 14CK BOD enabled 14CK + 4.1 ms Fast rising power 14CK + 65 ms Slowly rising power Reserved 29 ...
Page 30
... Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is chosen if the selcted clock source has a higher ATmega169V and clk are divided by a factor as shown in Table 13. ...
Page 31
... In this interval, 2 active clock edges are pro- duced. Here the previous clock period, and T2 is the period corresponding to the new prescaler setting. 2514H–AVR–05/03 CLKPS3 CLKPS2 CLKPS1 ATmega169V/L CLKPS0 Clock Division Factor 128 0 256 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 31 ...
Page 32
... The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s purpose recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after wak- ing up. ATmega169V/L 32 Bit – ...
Page 33
... TIMSK2, and the Global Interrupt Enable bit in SREG is set. It can also wake up from an LCD controller interrupt. If neither Timer/Counter2 nor the LCD controller is running, Power-down mode is rec- ommended instead of Power-save mode. 2514H–AVR–05/03 , and clk , while allowing the other clocks to run. CPU FLASH ATmega169V/L and clk , while allowing the CPU FLASH I ...
Page 34
... Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Ref- erence will be enabled, independent of sleep mode. Refer to “Analog Comparator” on page 189 for details on how to configure the Analog Comparator. ATmega169V/L 34 Oscillators INT0 ...
Page 35
... There are three alternative ways to disable the OCD system: • • • 2514H–AVR–05/03 ) and the ADC clock (clk I input pin can cause significant current even in active CC Disable the OCDEN Fuse. Disable the JTAGEN Fuse. Write one to the JTD bit in MCUCSR. ATmega169V/L ) are stopped, the input buff- ADC / ...
Page 36
... Reset Sources The ATmega169 has five sources of reset: • • • • • ATmega169V/L 36 Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V ). POT External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length ...
Page 37
... Voltage (falling) V RESET Pin Threshold Voltage RST Minimum pulse width on t RST RESET Pin 1. The Power-on Reset will not work unless the supply voltage has been below V (falling) ATmega169V/L DATA BUS MCU Status Register (MCUSR) Delay Counters CK TIMEOUT Condition Min Typ ...
Page 38
... Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after V again, without any delay, when V Figure 15. MCU Start-up, RESET Tied to V Figure 16. MCU Start-up, RESET Extended Externally ATmega169V/L 38 decreases below the detection level ...
Page 39
... RST – has expired. TOUT = /2. BOT- BOT HYST Typ V Max V BOT BOT BOT BOD Disabled 1.8 2.7 4.3 Reserved = V CC using BODLEVEL = 110 for ATmega169V Min Typ Max Units V during the BOT drops CC and Units mV µs 39 ...
Page 40
... This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset writing a logic zero to the flag. ATmega169V Figure 18), the delay counter starts the MCU after the Time- BOT+ has expired ...
Page 41
... ACBG bit in ACSR). Symbol Parameter Bandgap reference voltage V BG Bandgap reference start-up time t BG Bandgap reference current I BG consumption 1. Values are guidelines only. Actual values are TBD. ATmega169V/L (1) Condition Min Typ Max V = 2.7V, CC 1.0 1.1 1 25° ...
Page 42
... WDTON as shown in Table 20. Refer to “Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 44 for details. Table 20. WDT Configuration as a Function of the Fuse Settings of WDTON Figure 20. Watchdog Timer ATmega169V levels. By controlling the Watchdog Timer prescaler, the Watchdog Reset CC ...
Page 43
... WDP0 Oscillator Cycles 16K cycles 32K cycles 64K cycles 128K cycles 256K cycles 512K cycles 1,024K cycles 2,048K cycles ATmega169V WDCE WDE WDP2 WDP1 WDP0 R/W R/W R/W R/W R Typical Time-out Typical Time-out 3. 17.1 ms 34.3 ms 68.5 ms 0.14 s 0.27 s 0.55 s 1.1 s 2.2 s WDTCR = 5 ...
Page 44
... Safety Level 2 In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A timed sequence is needed when changing the Watchdog Time-out period. To change the Watchdog Time-out, the following procedure must be followed: ATmega169V/L 44 (1) Assembly Code Example WDT_off: ...
Page 45
... Within the next four clock cycles, in the same operation, write the WDP bits as 2514H–AVR–05/03 WDE always is set, the WDE must be written to one to start the timed sequence. desired, but with the WDCE bit cleared. The value written to the WDE bit is irrelevant. ATmega169V/L 45 ...
Page 46
... Interrupts This section describes the specifics of the interrupt handling as performed in ATmega169. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 12. Interrupt Vectors in Table 22. Reset and Interrupt Vectors ATmega169 Notes: ATmega169V/L 46 Vector Program (2) No. Address Source (1) 1 0x0000 ...
Page 47
... SPL,r16 0x0032 sei 0x0033 <instr> xxx ... ... ... ... ATmega169V/L (1) Interrupt Vectors Start Address 0x0002 Boot Reset Address + 0x0002 0x0002 Boot Reset Address + 0x0002 Comments ; Reset Handler ; IRQ0 Handler ; PCINT0 Handler ; PCINT0 Handler ; Timer2 Compare Handler ; Timer2 Overflow Handler ...
Page 48
... Reset and Interrupt Vector Addresses is: When the BOOTRST Fuse is programmed and the Boot section size set to 2K bytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: ATmega169V/L 48 Address ...
Page 49
... Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is pro- gramed, interrupts are disabled while executing from the Boot Loader section. Refer to the section “Boot Loader Support – Read-While-Write Self-Programming” on page 252 for details on Boot Lock bits. ATmega169V/L Comments ; Reset handler ; IRQ0 Handler ...
Page 50
... The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below. ATmega169V/L 50 Assembly Code Example Move_interrupts: ...
Page 51
... How each alternate function interferes with the port pin is described in “Alternate Port Functions” on page 56. Refer to the individual module sections for a full description of the alternate functions. 2514H–AVR–05/03 and Ground as indicated in Figure 21. Refer to “Electrical Characteristics” on page CC Pxn C pin ATmega169V Logic See Figure "General Digital I/O" for Details 51 ...
Page 52
... If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an out- put pin, the port pin is driven low (zero). ATmega169V/L 52 (1) Pxn ...
Page 53
... Input Input Output Output SYSTEM CLK INSTRUCTIONS XXX SYNC LATCH PINxn r17 ATmega169V/L Pull-up Comment No Tri-state (Hi-Z) Pxn will source current if ext. pulled Yes low. No Tri-state (Hi-Z) No Output Low (Sink) No Output High (Source) pd,max XXX in r17, PINx 0x00 t pd, max t ...
Page 54
... Figure 24. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is 1 system clock period. Figure 24. Synchronization when Reading a Software Assigned Pin Value ATmega169V/L 54 SYSTEM CLK r16 INSTRUCTIONS ...
Page 55
... For the assembly program, two temporary registers are used to minimize the time from pull-ups are set on pins and 7, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers. /2. CC ATmega169V/L 55 ...
Page 56
... Figure 22 can be overrid- den by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR micro- controller family. ATmega169V GND is not recommended, since this may cause CC ...
Page 57
... Pxn, PORT TOGGLE OVERRIDE ENABLE 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk , SLEEP, and PUD are common to all ports. All other signals are unique for each I/O pin. ATmega169V/L PUD Q D DDxn Q ...
Page 58
... Table 25. Generic Description of Overriding Signals for Alternate Functions The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details. ATmega169V/L 58 Signal Name Full Name Description ...
Page 59
... COM1 (LCD Back Plane 1) PA0 COM0 (LCD Back Plane 0) Signal Name PA7/SEG3 PUOE LCDEN PUOV 0 DDOE LCDEN DDOV 0 PVOE 0 PVOV 0 PTOE – DIEOE LCDEN DIEOV 0 DI – AIO SEG3 ATmega169V PUD – – IVSEL IVCE R R PA6/SEG2 PA5/SEG1 PA4/SEG0 LCDEN LCDEN LCDEN ...
Page 60
... Timer/Counter2 Output Compare A. The pin has to be configured as an output (DDB7 set (one)) to serve this function. The OC2A pin is also the output pin for the PWM mode timer function. PCINT15, Pin Change Interrupt source 15: The PB7 pin can serve as an external inter- rupt source. ATmega169V/L 60 Signal Name PA3/COM3 PA2/COM2 PUOE LCDEN • ...
Page 61
... When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB2. When the pin is forced input, the pull-up can still be controlled by the PORTB2 bit. PCINT10, Pin Change Interrupt Source 10: The PB2 pin can serve as an external inter- rupt source. 2514H–AVR–05/03 ATmega169V/L 61 ...
Page 62
... Table 30 and Table 31 relate the alternate functions of Port B to the overriding signals shown in Figure 25 on page 57. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. Table 30. Overriding Signals for Alternate Functions in PB7..PB4 ATmega169V/L 62 Signal PB7/OC2A/ PB6/OC1B/ ...
Page 63
... SEG8 (LCD Front Plane 8) PC3 SEG9 (LCD Front Plane 9) PC2 SEG10 (LCD Front Plane 10) PC1 SEG11 (LCD Front Plane 11) PC0 SEG12 (LCD Front Plane 12) ATmega169V/L PB1/SCK/ PB0/SS/ PCINT9 PCINT8 SPE • MSTR SPE • MSTR PORTB1 • PUD PORTB0 • PUD SPE • ...
Page 64
... Table 33 and Table 34 relate the alternate functions of Port C to the overriding signals shown in Figure 25 on page 57. Table 33. Overriding Signals for Alternate Functions in PC7..PC4 Table 34. Overriding Signals for Alternate Functions in PC3..PC0 ATmega169V/L 64 Signal Name PC7/SEG5 PC6/SEG6 PUOE LCDEN LCDEN PUOV ...
Page 65
... SEG16 (LCD front plane 16) PD5 SEG17 (LCD front plane 17) PD4 SEG18 (LCD front plane 18) PD3 SEG19 (LCD front plane 19) PD2 SEG20 (LCD front plane 20) PD1 INT0/SEG21 (External Interrupt0 Input or LCD front plane 21) PD0 ICP1/SEG22 (Timer/Counter1 Input Capture pin or LCD front plane 22) ATmega169V/L 65 ...
Page 66
... Table 36 and Table 37 relates the alternate functions of Port D to the overriding signals shown in Figure 25 on page 57. Table 36. Overriding Signals for Alternate Functions PD7..PD4 Table 37. Overriding Signals for Alternate Functions in PD3..PD0 ATmega169V/L 66 Signal Name PD7/SEG15 PD6/SEG16 PUOE LCDEN • LCDEN • ...
Page 67
... Pin Change Interrupt4) PE3 AIN1/PCINT3 (Analog Comparator Negative Input or Pin Change Interrupt3) XCK/AIN0/ PCINT2 (USART External Clock or Analog Comparator Positive Input PE2 or Pin Change Interrupt2) PE1 TXD/PCINT1 (USART Transmit Pin or Pin Change Interrupt1) PE0 RXD/PCINT0 (USART Receive Pin or Pin Change Interrupt0) ATmega169V/L 67 ...
Page 68
... PCINT0, Pin Change Interrupt Source 0: The PE0 pin can serve as an external interrupt source. Table 39 and Table 40 relates the alternate functions of Port E to the overriding signals shown in Figure 25 on page 57. Table 39. Overriding Signals for Alternate Functions PE7..PE4 Note: ATmega169V/L 68 Signal PE6/DO/ Name PE7/PCINT7 ...
Page 69
... ADC5/TMS (ADC input channel 5 or JTAG Test mode Select) PF4 ADC4/TCK (ADC input channel 4 or JTAG Test ClocK) PF3 ADC3 (ADC input channel 3) PF2 ADC2 (ADC input channel 2) PF1 ADC1 (ADC input channel 1) PF0 ADC0 (ADC input channel 0) ATmega169V/L PE1/TXD/ PCINT1 PE0/RXD/PCINT0 TXEN RXEN 0 PORTE0 • PUD TXEN RXEN 1 ...
Page 70
... TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG inter- face is enabled, this pin can not be used as an I/O pin. • ADC3 - ADC0 – Port F, Bit 3:0 Analog to Digital Converter, Channel 3-0. Table 42. Overriding Signals for Alternate Functions in PF7..PF4 ATmega169V/L 70 Signal Name PF7/ADC7/TDI ...
Page 71
... ADC3 INPUT ADC2 INPUT Port Pin Alternate Function PG4 T0/SEG23 (Timer/Counter0 Clock Input or LCD Front Plane 23) PG3 T1/SEG24 (Timer/Counter1 Clock Input or LCD Front Plane 24) PG2 SEG4 (LCD Front Plane 4) PG1 SEG13 (LCD Front Plane 13) PG0 SEG14 (LCD Front Plane 14) ATmega169V/L PF1/ADC1 PF0/ADC0 – ...
Page 72
... Table 44 and Table 45 relates the alternate functions of Port G to the overriding signals shown in Figure 25 on page 57. Table 45. Overriding Signals for Alternate Functions in PG4 Table 46. Overriding Signals for Alternate Functions in PG3:0 ATmega169V/L 72 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE – ...
Page 73
... Initial Value N/A N/A N/A Bit PORTC7 PORTC6 PORTC5 Read/Write R/W R/W R/W Initial Value Bit DDC7 DDC6 DDC5 Read/Write R/W R/W R/W Initial Value ATmega169V PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 R/W R/W R/W R DDA4 DDA3 DDA2 DDA1 DDA0 R/W R/W R/W R ...
Page 74
... Port D Input Pins Address – PIND Port E Data Register – PORTE Port E Data Direction Register – DDRE Port E Input Pins Address – PINE Port F Data Register – PORTF Port F Data Direction Register – DDRF ATmega169V/L 74 Bit PINC7 PINC6 PINC5 Read/Write R/W ...
Page 75
... Read/Write Initial Value Bit – – – Read/Write Initial Value Bit – – – Read/Write Initial Value ATmega169V PINF4 PINF3 PINF2 PINF1 PINF0 R/W R/W R/W R/W N/A N/A N/A N PORTG4 PORTG3 PORTG2 PORTG1 PORTG0 R/W R/W R/W R DDG4 ...
Page 76
... If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. Table 47. Interrupt 0 Sense Control ATmega169V/L 76 Bit – ...
Page 77
... Alternatively, the flag can be cleared by writing a logical one to it. 2514H–AVR–05/03 Bit PCIE1 PCIE0 – Read/Write R/W R/W R Initial Value Bit PCIF1 PCIF0 – Read/Write R/W R/W R Initial Value ATmega169V – – – – INT0 R – – – – INTF0 R R ...
Page 78
... Each PCINT7..0 bit selects whether pin change interrupt is enabled on the correspond- ing I/O pin. If PCINT7..0 is set and the PCIE0 bit in EIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled. ATmega169V/L 78 Bit 7 ...
Page 79
... Frequency Generator External Event Counter 10-bit Clock Prescaler Overflow and Compare Match Interrupt Sources (TOV0 and OCF0A) count clear Control Logic direction BOTTOM Timer/Counter TCNTn = 0 = OCRn ). T0 ATmega169V/L TCCRn Clock Select clk Tn Edge Detector TOP ( From Prescaler ) = 0xFF Waveform Generation TOVn (Int.Req.) Tn OCn (Int ...
Page 80
... Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 27 shows a block diagram of the counter and its surroundings. Figure 27. Counter Unit Block Diagram Signal description (internal signals): ATmega169V/L 80 BOTTOM The counter reaches the BOTTOM when it becomes 0x00. MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255) ...
Page 81
... Figure 28 shows a block diagram of the Output Compare unit. Figure 28. Output Compare Unit, Block Diagram 2514H–AVR–05/03 ). clk can be generated from an external or internal present or not. A CPU write overrides (has T0 DATA BUS OCRnx = (8-bit Comparator ) top bottom Waveform Generator FOCn WGMn1:0 ATmega169V/L TCNTn OCFnx (Int.Req.) OCnx COMnX1:0 81 ...
Page 82
... Output Compare (FOC0A) strobe bits in Normal mode. The OC0A Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM0A1:0 bits are not double buffered together with the compare value. Changing the COM0A1:0 bits will take effect immediately. ATmega169V/L 82 2514H–AVR–05/03 ...
Page 83
... A change of the COM0A1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC0A strobe bits. 2514H–AVR–05/03 COMnx1 Waveform COMnx0 D Q Generator FOCn OCnx D Q PORT D Q DDR clk I/O ATmega169V/L 1 OCn Pin 0 83 ...
Page 84
... TOP value. However, changing TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written ATmega169V/L 84 TCNTn ...
Page 85
... OCR0A and TCNT0. Figure 31. Fast PWM Mode, Timing Diagram 2514H–AVR–05/ when OCR0A is set to zero (0x00). The waveform frequency OC0 clk_I OCnx TCNTn OCn OCn Period ATmega169V/L f clk_I/O ------------------------------------------------- - OCRnx OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set (COMnx1 (COMnx1 ...
Page 86
... PWM mode is shown on Figure 32. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes repre- sent compare matches between OCR0A and TCNT0. ATmega169V clk_I/O ...
Page 87
... OCR0A changes its value from MAX, like in Figure 32. When the OCR0A value is MAX the OCn pin value is the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-counting Compare Match. ATmega169V/L OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set ...
Page 88
... Figure 34. Timer/Counter Timing Diagram, with Prescaler (f Figure 35 shows the setting of OCF0A in all modes except CTC mode. Figure 35. Timer/Counter Timing Diagram, Setting of OCF0A, with Prescaler (f ATmega169V/L 88 The timer starts counting from a value higher than the one in OCR0A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up ...
Page 89
... Operation” on page 84. 2514H–AVR–05/03 /8) clk_I/O clk I/O clk Tn (clk /8) I/O TCNTn TOP - 1 (CTC) OCRnx OCFnx Bit FOC0A WGM00 COM0A1 Read/Write W R/W R/W Initial Value ATmega169V/L TOP BOTTOM TOP COM0A0 WGM01 CS02 CS01 CS00 R/W R/W R/W R BOTTOM + 1 0 TCCR0 R ...
Page 90
... WGM01:0 bits are set to a normal or CTC mode (non-PWM). Table 50. Compare Output Mode, non-PWM Mode Table 51 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM mode. Table 51. Compare Output Mode, Fast PWM Mode Note: ATmega169V/L 90 WGM01 WGM00 Timer/Counter Mode ...
Page 91
... I clk /256 (From prescaler) I clk /1024 (From prescaler) I External clock source on T0 pin. Clock on falling edge External clock source on T0 pin. Clock on rising edge. Bit Read/Write R/W R/W R/W Initial Value ATmega169V/L ( TCNT0[7:0] R/W R/W R/W R/W R TCNT0 91 ...
Page 92
... Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 ( Tim er /Co u nte flo w In ter Timer/Counter0 Overflow interrupt is executed. In phase correct PWM mode, this bit is set when Timer/Counter0 changes counting direction at 0x00. ATmega169V/L 92 Bit 7 6 ...
Page 93
... The T1/T0 pin is sampled once every system clock cycle by the pin syn The latch is transparent in the high period of the internal clk I clk I/O Synchronization ATmega169V/L ). Alternatively, one of four taps from the pres- /1024. CLK_I/O /clk pulse for each positive (CSn2 neg Edge Detector < f /2) given a 50/50% duty cycle. Since ExtClk ...
Page 94
... When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this pres- caler will affect both timers. ATmega169V/L 94 clk_I/O clk ...
Page 95
... Double Buffered Output Compare Registers One Input Capture Unit Input Capture Noise Canceler Clear Timer on Compare Match (Auto Reload) Glitch-free, Phase Correct Pulse Width Modulator (PWM) Variable PWM Period Frequency Generator External Event Counter Four independent interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1) ATmega169V/L 95 ...
Page 96
... The double buffered Output Compare Registers (OCR1A/B) are compared with the Timer/Counter value at all time. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pin (OC1A/B). See “Output Compare Units” on page 104.. The compare match event will ATmega169V/L 96 Count Clear ...
Page 97
... All 16-bit Timer/Counter related I/O Register address locations, including Timer Interrupt Registers. Bit locations inside all 16-bit Timer/Counter Registers, including Timer Interrupt Registers. Interrupt Vectors. PWM10 is changed to WGM10. PWM11 is changed to WGM11. CTC1 is changed to WGM12. FOC1A and FOC1B are added to TCCR1C. WGM13 is added to TCCR1B. ATmega169V/L 97 ...
Page 98
... Timer Registers, then the result of the access outside the interrupt will be corrupted. ATmega169V/L 98 (1) Assembly Code Examples ... ...
Page 99
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. ATmega169V/L 99 ...
Page 100
... If writing to more than one 16-bit register where the high byte is the same for all registers Byte Register written, then the high byte only needs to be written once. However, note that the same rule of atomic operation described previously also applies in this case. ATmega169V/L 100 (1) Assembly Code Example TIM16_WriteTCNT1: ...
Page 101
... Clear TCNT1 (set all bits to zero). clk Timer/Counter clock TOP Signalize that TCNT1 has reached maximum value. BOTTOM Signalize that TCNT1 has reached minimum value (zero). ). The clk T 1 ATmega169V/L TOVn (Int.Req.) Clock Select Count Edge Detector Clear clk Tn Control Logic ( From Prescaler ) ...
Page 102
... When the low byte is read the high byte is copied into the high byte temporary register (TEMP). When the CPU reads the ICR1H I/O location it will access the TEMP Register. ATmega169V/L 102 DATA BUS ...
Page 103
... ICR1 Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt handler is used). 2514H–AVR–05/03 ATmega169V/L 103 ...
Page 104
... The OCR1x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR1x Buffer Register, and if double buffering is disabled the CPU will access the OCR1x directly. The content of the OCR1x ATmega169V/L 104 DATA BUS ...
Page 105
... Output Compare (FOC1x) strobe bits in Normal mode. The OC1x Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM1x1:0 bits are not double buffered together with the compare value. Changing the COM1x1:0 bits will take effect immediately. 2514H–AVR–05/03 ATmega169V/L 105 ...
Page 106
... The design of the Output Compare pin logic allows initialization of the OC1x state before the output is enabled. Note that some COM1x1:0 bit settings are reserved for certain modes of operation. See “16-bit Timer/Counter Register Description” on page 117. The COM1x1:0 bits have no effect on the Input Capture unit. ATmega169V/L 106 COMnx1 Waveform ...
Page 107
... The Output Compare units can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. 2514H–AVR–05/03 ATmega169V/L 107 ...
Page 108
... The N variable represents the prescaler factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the TOV1 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x0000. ATmega169V/L 108 TCNTn OCnA (Toggle) ...
Page 109
... TOP and com- pare values. 2514H–AVR–05/03 R FPWM TCNTn OCnx OCnx Period ATmega169V/L log TOP + 1 = ---------------------------------- - log 2 OCRnx / TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn ...
Page 110
... This applies only if OCR1A is used to define the TOP value (WGM13:0 = 15). The wave- form generated will have a maximum frequency of f zero (0x0000). This feature is similar to the OC1A toggle in CTC mode, except the dou- ble buffer feature of the Output Compare unit is enabled in the fast PWM mode. ATmega169V/L 110 f clk_I/O ...
Page 111
... OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a compare match occurs. Figure 46. Phase Correct PWM Mode, Timing Diagram 2514H–AVR–05/03 R PCPWM TCNTn OCnx OCnx Period 1 ATmega169V/L log 1 TOP + = ---------------------------------- - log 2 OCRnx/TOP Update and OCnA Interrupt Flag Set ...
Page 112
... BOTTOM the output will be continuously low and if set equal to TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 11) and COM1A1 the OC1A output will toggle with a 50% duty cycle. ATmega169V/L 112 f clk_I/O ...
Page 113
... OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a com- pare match occurs. Figure 47. Phase and Frequency Correct PWM Mode, Timing Diagram 2514H–AVR–05/03 R PFCPW M TCNTn OCnx OCnx Period 1 2 ATmega169V/L log 1 TOP + = ---------------------------------- - log 2 OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) ...
Page 114
... BOTTOM the output will be continuously low and if set equal to TOP the output will be set to high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCR1A is used to define the TOP value (WGM13 and COM1A1 the OC1A output will toggle with a 50% duty cycle. ATmega169V/L 114 f clk_I/O ...
Page 115
... BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 Flag at BOTTOM. 2514H–AVR–05/03 clk I/O clk Tn (clk /1) I/O TCNTn OCRnx - 1 OCRnx OCFnx clk I/O clk Tn (clk /8) I/O TCNTn OCRnx - 1 OCRnx OCRnx OCFnx ATmega169V therefore T1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCRnx + 1 OCRnx + 2 OCRnx Value /8) clk_I/O 115 ...
Page 116
... Figure 50. Timer/Counter Timing Diagram, no Prescaling Figure 51 shows the same timing data, but with the prescaler enabled. Figure 51. Timer/Counter Timing Diagram, with Prescaler (f ATmega169V/L 116 clk I/O clk Tn (clk /1) I/O TCNTn TOP - 1 (CTC and FPWM) TCNTn TOP - 1 (PC and PFC PWM) TOVn ...
Page 117
... COM1A1/COM1B1 COM1A0/COM1B0 special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In this case the compare match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 109. for more details. ATmega169V COM1B0 – – WGM11 WGM10 R R/W ...
Page 118
... Table 58. Modes of operation sup- ported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See “Modes of Operation” on page 107.). ATmega169V/L 118 (1) COM1A1/COM1B1 ...
Page 119
... CTC 0 1 (Reserved Fast PWM 1 1 Fast PWM Bit ICNC1 ICES1 – Read/Write R/W R/W R Initial Value ATmega169V/L Update of x TOP OCR1 at 0xFFFF Immediate 0x00FF TOP 0x01FF TOP 0x03FF TOP OCR1A Immediate 0x00FF TOP 0x01FF TOP 0x03FF TOP ICR1 BOTTOM OCR1A ...
Page 120
... FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1x1:0 bits that determine the effect of the forced compare. ATmega169V/L 120 CS12 CS11 ...
Page 121
... See “Accessing 16-bit Registers” on page 98. 2514H–AVR–05/03 Bit Read/Write R/W R/W R/W Initial Value Bit Read/Write R/W R/W R/W Initial Value Bit Read/Write R/W R/W R/W Initial Value ATmega169V TCNT1[15:8] TCNT1[7:0] R/W R/W R/W R/W R OCR1A[15:8] OCR1A[7:0] R/W R/W R/W R/W R ...
Page 122
... When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo- bally enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 46.) is executed when the TOV1 Flag, located in TIFR1, is set. ATmega169V/L 122 Bit 7 ...
Page 123
... TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. 2514H–AVR–05/03 Bit – – ICF1 Read/Write R R R/W Initial Value ATmega169V – – OCF1B OCF1A TOV1 R R R/W R/W R ...
Page 124
... TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock source the Timer/Counter uses to increment (or decre- ATmega169V/L 124 Single Channel Counter Clear Timer on Compare Match (Auto Reload) ...
Page 125
... TCNTn Control Logic direction bottom count Increment or decrement TCNT2 by 1. direction Selects between increment and decrement. clear Clear TCNT2 (set all bits to zero). clk Timer/Counter clock. T2 ATmega169V default equal to the MCU clock, clk T2 TOVn (Int.Req.) T/C clk Tn Oscillator Prescaler clk top ...
Page 126
... The max and bottom signals are used by the Waveform Generator for handling the spe- cial cases of the extreme values in some modes of operation (“Modes of Operation” on page 129). Figure 54 shows a block diagram of the Output Compare unit. Figure 54. Output Compare Unit, Block Diagram ATmega169V/L 126 top Signalizes that TCNT2 has reached maximum value. bottom Signalizes that TCNT2 has reached minimum value (zero) ...
Page 127
... Output Compare (FOC2A) strobe bit in Normal mode. The OC2A Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM2A1:0 bits are not double buffered together with the compare value. Changing the COM2A1:0 bits will take effect immediately. 2514H–AVR–05/03 ATmega169V/L 127 ...
Page 128
... PWM mode, refer to Table 63 on page 136, and for phase correct PWM refer to Table 64 on page 136. A change of the COM2A1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC2A strobe bits. ATmega169V/L 128 COMnx1 Waveform COMnx0 ...
Page 129
... CTC mode does not have the double buffering feature. If the new value written to OCR2A is lower than the current value of TCNT2, the counter will miss the 2514H–AVR–05/03 TCNTn OCnx (Toggle) Period 1 2 ATmega169V/L OCnx Interrupt Flag Set (COMnx1 129 ...
Page 130
... The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2A and TCNT2. Figure 57. Fast PWM Mode, Timing Diagram ATmega169V/L 130 = f /2 when OCR2A is set to zero (0x00). The waveform fre- ...
Page 131
... PWM mode is shown on Figure 58. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes repre- sent compare matches between OCR2A and TCNT2. 2514H–AVR–05/03 ATmega169V/L f clk_I ...
Page 132
... At the very start of period 2 in Figure 58 OCn has a transition from high to low even though there is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a transition without Compare Match. • ATmega169V/L 132 TCNTn OCnx ...
Page 133
... Compare Match and hence the OCn change that would have happened on the way up therefore shown as a clock enable signal. In asynchronous mode, clk T2 clk I/O clk Tn (clk /1) I/O TCNTn MAX - 1 TOVn clk I/O clk Tn (clk /8) I/O TCNTn MAX - 1 TOVn ATmega169V/L MAX BOTTOM BOTTOM + 1 /8) clk_I/O MAX BOTTOM BOTTOM + 1 should I/O 133 ...
Page 134
... Figure 61. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (f Figure 62 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode. Figure 62. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (f ATmega169V/L 134 clk I/O clk Tn (clk /8) I/O TCNTn OCRnx - 1 OCRnx OCRnx ...
Page 135
... PWM, Phase Correct CTC Fast PWM 1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 def- initions. However, the functionality and location of these bits are compatible with previous versions of the timer. ATmega169V COM2A0 WGM21 CS22 CS21 CS20 R/W R/W ...
Page 136
... PWM mode. Table 63. Compare Output Mode, Fast PWM Mode Note: Table 64 shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase correct PWM mode. Table 64. Compare Output Mode, Phase Correct PWM Mode Note: ATmega169V/L 136 COM2A1 COM2A0 Description 0 0 Normal port operation, OC2A disconnected. ...
Page 137
... R/W R/W R/W Initial Value Bit Read/Write R/W R/W R/W Initial Value ATmega169V/L Description No clock source (Timer/Counter stopped). clk /(No prescaling) T2S clk /8 (From prescaler) T2S clk /32 (From prescaler) T2S clk /64 (From prescaler) T2S clk /128 (From prescaler) T2S clk /256 (From prescaler) ...
Page 138
... The mechanisms for reading TCNT2, OCR2A, and TCCR2A are different. When read- ing TCNT2, the actual timer value is read. When reading OCR2A or TCCR2A, the value in the temporary storage register is read. ATmega169V/L 138 Bit – ...
Page 139
... Power-down or Standby mode. The contents of all Timer/Counter2 Registers must be considered lost after a wake-up from Power- down or Standby mode due to unstable clock signal upon start-up, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin. ATmega169V/L 139 ...
Page 140
... Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed verflo w in Timer/Coun ter2 occurs, i.e ., when the set Timer/Counter2 Interrupt Flag Register – TIFR2. ATmega169V/L 140 Description of wake up from Power-save or ADC Noise Reduction mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value ...
Page 141
... TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2A ( Tim er /Co u nte flo w In ter Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00. 2514H–AVR–05/03 Bit – – – Read/Write Initial Value ATmega169V – – – OCF2A TOV2 R/W R ...
Page 142
... The bit will not be cleared by hardware if the TSM bit is set. Refer to the description of the “Bit 7 – TSM: Timer/Counter Synchronization Mode” on page 94 for a description of the Timer/Counter Synchronization mode. ATmega169V/L 142 clk clk ...
Page 143
... LSB First or MSB First Data Transfer Seven Programmable Bit Rates End of Transmission Interrupt Flag Write Collision Flag Protection Wake-up from Idle Mode Double Speed (CK/2) Master SPI Mode (1) DIVIDER /2/4/8/16/32/64/128 1. Refer to Figure 1 on page 2, and Table 29 on page 60 for SPI pin placement. ATmega169V/L 143 ...
Page 144
... When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 66. For more details on automatic port overrides, refer to “Alternate Port Functions” on page 56. Table 66. SPI Pin Overrides Note: ATmega169V/L 144 /4. osc (1) Pin Direction, Master SPI ...
Page 145
... Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); } void SPI_MasterTransmit(char cData Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) ; } 1. The example code assumes that the part specific header file is included. ATmega169V/L 145 ...
Page 146
... The following code examples show how to initialize the SPI as a Slave and how to per- form a simple reception. Note: ATmega169V/L 146 (1) Assembly Code Example SPI_SlaveInit: ; Set MISO output, all others input ldi r17,(1<<DD_MISO) out DDR_SPI,r17 ; Enable SPI ldi r17,(1<<SPE) ...
Page 147
... SPI becoming a Slave, the MOSI and SCK pins become inputs. SREG is set, the interrupt routine will be executed. Bit SPIE SPE DORD Read/Write R/W R/W R/W Initial Value ATmega169V MSTR CPOL CPHA SPR1 SPR0 R/W R/W R/W R/W R ...
Page 148
... These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency f Table 69. Relationship Between SCK and the Oscillator Frequency ATmega169V/L 148 CPOL Leading Edge ...
Page 149
... Reading the register causes the Shift Register Receive buffer to be read. 2514H–AVR–05/03 Bit SPIF WCOL – Read/Write Initial Value lower. osc Bit MSB Read/Write R/W R/W R/W Initial Value ATmega169V – – – – SPI2X R LSB R/W R/W R/W R/W R/W ...
Page 150
... SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing Table 67 and Table 68, as done below: Table 70. CPOL Functionality Figure 66. SPI Transfer Format with CPHA = 0 Figure 67. SPI Transfer Format with CPHA = 1 ATmega169V/L 150 Leading Edge CPOL=0, CPHA=0 Sample (Rising) ...
Page 151
... UBRR[H:L] BAUD RATE GENERATOR UDR (Transmit) TRANSMIT SHIFT REGISTER RECEIVE SHIFT REGISTER UDR (Receive) UCSRA 1. Refer to Figure 1 on page 2, Table 36 on page 66, and Table 30 on page 62 for USART pin placement. ATmega169V/L Clock Generator OSC SYNC LOGIC PIN XCK CONTROL Transmitter TX CONTROL ...
Page 152
... Data Direction Register for the XCK pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCK pin is only active when using synchronous mode. Figure 69 shows a block diagram of the clock generation logic. ATmega169V/L 152 Bit locations inside all USART Registers. Baud Rate Generation. ...
Page 153
... Clock output to XCK pin (Internal Signal). Used for synchronous master operation. fosc XTAL pin frequency (System Clock loaded with the UBRR value each time the counter has counted down osc /(UBRR+1)). The Transmitter divides the baud rate generator clock output osc ATmega169V/L U2X / DDR_XCK ...
Page 154
... Receiver. This process introduces a two CPU clock period delay and therefore the max- imum external XCK clock frequency is limited by the following equation: Note that f mended to add some margin to avoid possible loss of data due to frequency variations. ATmega169V/L 154 Equation for Calculating Operating Mode ...
Page 155
... RxD / TxD UCPOL = 0 XCK RxD / TxD 1 start bit data bits no, even or odd parity bit stop bits (IDLE Start bit, always low. (n) Data bits (0 to 8). P Parity bit. Can be odd or even. ATmega169V/L Sample Sample FRAME 4 [5] [6] [7] [8] [P] Sp1 [Sp2] (St / IDLE) 155 ...
Page 156
... TXC Flag can be used to check that the Transmitter has completed all transfers, and the RXC Flag can be used to check that there are no unread data in the receive buffer. Note that the TXC Flag must be cleared before each transmission (before UDR is written used for this purpose. ATmega169V/L 156 Sp Stop bit, always high. ...
Page 157
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. ATmega169V/L 157 ...
Page 158
... The function simply waits for the transmit buffer to be empty by checking the UDRE Flag, before loading it with new data to be transmitted. If the Data Register Empty inter- rupt is utilized, the interrupt routine writes the data into the buffer. ATmega169V/L 158 (1) Assembly Code Example USART_Transmit: ...
Page 159
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. ATmega169V/L 159 ...
Page 160
... The disabling of the Transmitter (setting the TXEN to zero) will not become effective until ongoing and pending transmissions are completed, i.e., when the Transmit Shift Register and Transmit Buffer Register do not contain data to be transmitted. When dis- abled, the Transmitter will no longer override the TxD pin. ATmega169V/L 160 2514H–AVR–05/03 ...
Page 161
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. ATmega169V/L 161 ...
Page 162
... UDR I/O location will change the state of the receive buffer FIFO and consequently the TXB8, FE, DOR and UPE bits, which all are stored in the FIFO, will change. The following code example shows a simple USART receive function that handles both nine bit characters and the status bits. Note: ATmega169V/L 162 (1) Assembly Code Example USART_Receive: ...
Page 163
... UCSRA. For more details see “Parity Bit Calculation” on page 156 and “Parity Checker” on page 164. 2514H–AVR–05/03 extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. ATmega169V/L 163 ...
Page 164
... The data recovery logic samples and low pass filters each incoming bit, thereby improv- ing the noise immunity of the Receiver. The asynchronous reception operational range depends on the accuracy of the internal baud rate clock, the rate of the incoming frames, and the frame size in number of bits. ATmega169V/L 164 (1) Assembly Code Example ...
Page 165
... RxD pin. The recovery process is then repeated until a complete frame is received. Including the first stop bit. Note that the Receiver only uses the first stop bit of a frame. 2514H–AVR–05/03 RxD IDLE Sample (U2X = Sample (U2X = RxD Sample (U2X = Sample (U2X = ATmega169V/L START BIT ...
Page 166
... The following equations can be used to calculate the ratio of the incoming data rate and internal receiver baud rate Table 72 and Table 73 list the maximum receiver baud rate error that can be tolerated. Note that Normal Speed mode has higher toleration of baud rate variations. ATmega169V/L 166 RxD Sample (U2X = ...
Page 167
... ATmega169V/L Recommended Max (%) Max Total Error (%) Receiver Error (%) +6.67/-6.8 +5.79/-5.88 +5.11/-5.19 +4.58/-4.54 +4.14/-4.19 +3.78/-3.83 Recommended Max (%) Max Total Error (%) Receiver Error (%) +5.66/-5.88 +4.92/-5.08 +4 ...
Page 168
... Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCM bit. The MPCM bit shares the same I/O location as the TXC Flag and this might accidentally be cleared when using SBI or CBI instructions. ATmega169V/L 168 is set). frame. In the Slave MCUs, the RXC Flag in UCSRA will be set as normal. ...
Page 169
... The TXC Flag can generate a Transmit Complete interrupt (see description of the TXCIE bit). 2514H–AVR–05/03 Bit Read/Write R/W R/W R/W Initial Value Bit RXC TXC UDRE Read/Write R R/W R Initial Value ATmega169V RXB[7:0] TXB[7:0] R/W R/W R/W R/W R DOR UPE U2X MPCM R R ...
Page 170
... This bit enables the Multi-processor Communication mode. When the MPCM bit is writ- ten to one, all the incoming frames received by the USART Receiver that do not contain address information will be ignored. The Transmitter is unaffected by the MPCM setting. For more detailed information see “Multi-processor Communication Mode” on page 168. ATmega169V/L 170 2514H–AVR–05/03 ...
Page 171
... TXB8 is the ninth data bit in the character to be transmitted when operating with serial frames with nine data bits. Must be written before writing the low bits to UDR. 2514H–AVR–05/03 Bit RXCIE TXCIE UDRIE Read/Write R/W R/W R/W Initial Value ATmega169V RXEN TXEN UCSZ2 RXB8 TXB8 R/W R/W R ...
Page 172
... UPM0 setting mismatch is detected, the UPE Flag in UCSRA will be set. Table 75. UPM Bits Settings • Bit 3 – USBS: Stop Bit Select This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting. Table 76. USBS Bit Settings ATmega169V/L 172 Bit – ...
Page 173
... Rising XCK Edge 1 Falling XCK Edge Bit – – – Read/Write R/W R/W R/W Initial Value ATmega169V/L UCSZ0 Character Size 0 5-bit 1 6-bit 0 7-bit 1 8-bit 0 Reserved 1 Reserved 0 Reserved 1 9-bit Received Data Sampled (Input on RxD Pin) Falling XCK Edge Rising XCK Edge – ...
Page 174
... Max. 62.5 kbps 125 kbps 1. UBRR = 0, Error = 0.0% ATmega169V/L 174 BaudRate Error[%] ------------------------------------------------------- - 1 = 1.8432 MHz osc U2X = 0 U2X = 1 Error UBRR Error UBRR 0.2% 47 0.0% 95 0.2% 23 0.0% 47 ...
Page 175
... Mbps ATmega169V 7.3728 MHz osc U2X = 0 U2X = 1 Error UBRR Error UBRR 0.2% 191 0.0% 383 0.2% 95 0.0% 191 0.2% 47 0.0% 95 -0.8% 31 0. ...
Page 176
... Max. 0.5 Mbps 1 Mbps 1. UBRR = 0, Error = 0.0% ATmega169V/L 176 11.0592 f = MHz osc U2X = 0 U2X = 1 Error UBRR Error UBRR -0.1% 287 0.0% 575 0.2% 143 0.0% 287 0.2% 71 0.0% 143 0. ...
Page 177
... Mbps 2.304 Mbps ATmega169V 20.0000 MHz osc U2X = 0 U2X = 1 Error UBRR Error UBRR 0.0% 520 0.0% 1041 0.0% 259 0.2% 520 0.0% 129 0.2% 259 0. ...
Page 178
... The clock can be selected from three different sources: The USCK pin, Timer/Counter0 Compare Match or from software. ATmega169V/L 178 Two-wire Synchronous Data Transfer (Master or Slave, f Three-wire Synchronous Data Transfer (Master or Slave f ...
Page 179
... USITC bit in USICR. Figure 77. Three-wire Mode, Timing Diagram 2514H–AVR–05/03 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SLAVE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MASTER CYCLE ( Reference ) USCK USCK DO MSB MSB ATmega169V USCK DO DI USCK PORTxn LSB LSB E 179 ...
Page 180
... The second and third instructions clears the USI Counter Overflow Flag and the USI counter value. The fourth and fifth instruction set Three-wire mode, positive edge Shift Register clock, count at USITC strobe, and toggle USCK. The loop is repeated 16 times. ATmega169V/L 180 the protocol used, enables its output driver (mark A and B). The output is set up by writing the data to be transmitted to the Serial Data Register ...
Page 181
... USICR,r17 sts USICR,r16 ; LSB sts USICR,r17 lds r16,USIDR ret init: ldi r16,(1<<USIWM0)|(1<<USICS1) sts USICR,r16 ... SlaveSPITransfer: sts USIDR,r16 ldi r16,(1<<USIOIF) sts USISR,r16 SlaveSPITransfer_loop: lds r16, USISR sbrs r16, USIOIF rjmp SlaveSPITransfer_loop lds r16,USIDR ret ATmega169V/L 181 ...
Page 182
... The clock is generated by the master by toggling the USCK pin via the PORT Register. The data direction is not given by the physical layer. A protocol, like the one used by the TWI-bus, must be implemented to control the data flow. ATmega169V/L 182 Bit7 Bit6 ...
Page 183
... Slave enables its output. If the bit is set, a master read operation is in progress (i.e., the slave drives the SDA line) The slave can hold the SCL line low after the acknowledge (E). is given by the Master (F new start condition is given. SDA SCL Write( USISIF) ATmega169V DATA ACK ...
Page 184
... The output will be changed immediately when a new MSB written as long as the latch is open. The latch ensures that data input is sampled and data output is changed on opposite clock edges. ATmega169V/L 184 Bit 7 ...
Page 185
... USITC strobe bit. This feature is enabled by write a one to the USICLK bit while setting an external clock source (USICS1 = 1). 2514H–AVR–05/03 Bit USISIF USIOIF USIPF Read/Write R/W R/W R/W Initial Value ATmega169V USIDC USICNT3 USICNT2 USICNT1 USICNT0 R R/W R/W R ...
Page 186
... Data and clock inputs are not affected by the mode selected and will always have the same function. The counter and Shift Register can therefore be clocked externally, and data input sampled, even when outputs are disabled. The relations between USIWM1..0 and the USI operation is summarized in Table 83. ATmega169V/L 186 Bit 7 6 ...
Page 187
... SCL line is also held low when a counter overflow occurs, and is held low until the Counter Overflow Flag (USIOIF) is cleared. 1. The DI and USCK pins are renamed to Serial Data (SDA) and Serial Clock (SCL) respectively to avoid confusion between the modes of operation. ATmega169V/L (1) . 187 ...
Page 188
... When an external clock source is selected (USICS1 = 1) and the USICLK bit is set to one, writing to the USITC strobe bit will directly clock the 4-bit counter. This allows an early detection of when the transfer is done when operating as a master device. ATmega169V/L 188 Shift Register Clock ...
Page 189
... Refer to Figure 1 on page 2 and Table 28 on page 60 for Analog Comparator pin placement. Bit – ACME – Read/Write R R/W R Initial Value Bit ACD ACBG ACO Read/Write R/W R/W R Initial Value 0 0 N/A ATmega169V/L ( – – ADTS2 ADTS1 ADTS0 R R R/W R/W R ACI ACIE ACIC ACIS1 ACIS0 ...
Page 190
... The different settings are shown in Table 85. Table 85. ACIS1/ACIS0 Settings When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be dis- abled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed. ATmega169V/L 190 ACIS1 ACIS0 Interrupt Mode ...
Page 191
... Bit – – – Read/Write Initial Value ATmega169V/L Analog Comparator Negative Input AIN1 AIN1 ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 – – – AIN1D AIN0D R/W R DIDR1 ...
Page 192
... V connect this pin. Internal reference voltages of nominally 1.1V or AVCC are provided On-chip. The volt- age reference may be externally decoupled at the AREF pin by a capacitor for better noise performance. ATmega169V/L 192 10-bit Resolution 0.5 LSB Integral Non-linearity ± 2 LSB Absolute Accuracy 13 µ ...
Page 193
... ADC6 POS. ADC5 INPUT MUX ADC4 ADC3 DIFFERENTIAL AMPLIFIER + ADC2 - ADC1 ADC0 NEG. INPUT MUX ATmega169V/L ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS[2: ADC CTRL. & STATUS ADC DATA REGISTER REGISTER (ADCSRA) (ADCH/ADCL) TRIGGER SELECT PRESCALER CONVERSION LOGIC SAMPLE & HOLD ...
Page 194
... Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Run- ning mode, constantly sampling and updating the ADC Data Register. The first ATmega169V/L 194 ADTS[2:0] ...
Page 195
... Three additional CPU clock cycles are used for synchronization logic. When using Differential mode, along with Auto triggering from a source other than the 2514H–AVR–05/03 ADEN Reset START 7-BIT ADC PRESCALER CK ADPS0 ADPS1 ADPS2 ADC CLOCK SOURCE ATmega169V/L 195 ...
Page 196
... In Free Running mode, a new conversion will be started immediately after the conver- sion completes, while ADSC remains high. For a summary of conversion times, see Table 87. Figure 85. ADC Timing Diagram, First Conversion (Single Conversion Mode) Figure 86. ADC Timing Diagram, Single Conversion Figure 87. ADC Timing Diagram, Auto Triggered Conversion ATmega169V/L 196 Cycle Number ...
Page 197
... Normal conversions, single ended Auto Triggered conversions Normal conversions, differential is low will take the same amount of time as a single ended conversion (13 ADC ADC2 is high will take 14 ADC clock cycles due to the synchronization mecha- ADC2 ATmega169V/L Next Conversion Sign and MSB of Result LSB of Result Sample & ...
Page 198
... When switching to a differential gain channel, the first conversion result may have a poor accuracy due to the required settling time for the automatic offset cancellation cir- cuitry. The user should preferably disregard the first conversion result. ATmega169V/L 198 1. When ADATE or ADEN is cleared. ...
Page 199
... ADC Conversion Complete interrupt request will be generated when the ADC conversion completes. The CPU will remain in active mode until a new sleep command is executed. ATmega169V/L ) indicates the conversion range for the ADC. will result in codes close to 0x3FF through an internal amplifier. In ...
Page 200
... The user is advised to remove high frequency components with a low-pass filter before applying the signals as inputs to the ADC. Figure 89. Analog Input Circuitry ATmega169V/L 200 or less. If such a source is used, the sampling time will be negligible source I ...