DSPIC30F3010-30I/SO Microchip Technology, DSPIC30F3010-30I/SO Datasheet - Page 107
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DSPIC30F3010-30I/SO
Manufacturer Part Number
DSPIC30F3010-30I/SO
Description
IC DSPIC MCU/DSP 24K 28SOIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F3010-30ISO.pdf
(228 pages)
2.DSPIC30F3010-30ISO.pdf
(18 pages)
3.DSPIC30F3010-30ISO.pdf
(6 pages)
4.DSPIC30F3010-30ISO.pdf
(16 pages)
5.DSPIC30F3010-30ISO.pdf
(22 pages)
6.DSPIC30F3014-30IP.pdf
(244 pages)
Specifications of DSPIC30F3010-30I/SO
Program Memory Type
FLASH
Program Memory Size
24KB (8K x 24)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
20
Eeprom Size
1K x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
Maximum Clock Frequency
30 MHz
Data Ram Size
1 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300027, DM330011, DM300018, DM183021
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
DSPIC30F301030ISO
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F3010-30I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
15.1.5
The input clock to PTMR (F
options of 1:1, 1:4, 1:16, or 1:64, selected by control
bits PTCKPS<1:0> in the PTCON SFR. The prescaler
counter is cleared when any of the following occurs:
• a write to the PTMR register
• a write to the PTCON register
• any device Reset
The PTMR register is not cleared when PTCON is
written.
15.1.6
The match output of PTMR can optionally be post-
scaled through a 4-bit postscaler (which gives a 1:1 to
1:16 scaling).
The postscaler counter is cleared when any of the
following occurs:
• a write to the PTMR register
• a write to the PTCON register
• any device Reset
The PTMR register is not cleared when PTCON is written.
15.2
PTPER is a 15-bit register and is used to set the count-
ing period for the PWM time base. PTPER is a double
buffered register. The PTPER buffer contents are
loaded into the PTPER register at the following instants:
• Free Running and Single Shot modes: When the
• Up/Down Counting modes: When the PTMR
The value held in the PTPER buffer is automatically
loaded into the PTPER register when the PWM time
base is disabled (PTEN = 0).
The
Equation 15-1:
EQUATION 15-1:
If the PWM time base is configured for one of the Up/
Down Count modes, the PWM period will be twice the
value provided by Equation 15-1.
2004 Microchip Technology Inc.
Note: PWM period will be twice the value provided
by this equation when using center aligned modes.
PTMR register is reset to zero after a match with
the PTPER register.
register is zero.
PWM
PWM Period
T
PWM
PWM TIME BASE PRESCALER
PWM TIME BASE POSTSCALER
period
=
(PTMR Prescale Value)
T
PWM PERIOD
CY
can
•
(PTPER + 1)
be
OSC
determined
/4), has prescaler
using
Preliminary
The maximum resolution (in bits) for a given device
oscillator and PWM frequency can be determined using
Equation 15-2:
EQUATION 15-2:
15.3
Edge aligned PWM signals are produced by the module
when the PWM time base is in the Free Running or Sin-
gle Shot mode. For edge aligned PWM outputs, the out-
put has a period specified by the value in PTPER and a
duty cycle specified by the appropriate duty cycle regis-
ter (see Figure 15-3). The PWM output is driven active
at the beginning of the period (PTMR = 0) and is driven
inactive when the value in the duty cycle register
matches PTMR.
If the value in a particular duty cycle register is zero,
then the output on the corresponding PWM pin will be
inactive for the entire PWM period. In addition, the out-
put on the PWM pin will be active for the entire PWM
period if the value in the duty cycle register is greater
than the value held in the PTPER register.
FIGURE 15-3:
15.4
Center aligned PWM signals are produced by the mod-
ule when the PWM time base is configured in an Up/
Down Counting mode (see Figure 15-4).
The PWM compare output is driven to the active state
when the value of the duty cycle register matches the
value of PTMR and the PWM time base is counting
downwards (PTDIR = 1). The PWM compare output is
driven to the inactive state when the PWM time base is
counting upwards (PTDIR = 0) and the value in the
PTMR register matches the duty cycle value.
PTPER
0
Resolution =
Edge Aligned PWM
Center Aligned PWM
PTMR
Value
Duty Cycle
Period
PWM RESOLUTION
EDGE ALIGNED PWM
log (2
New Duty Cycle Latched
dsPIC30F
log (2)
•
T
PWM
DS70082G-page 105
/ T
CY
)