PIC18LF6310-I/PT Microchip Technology, PIC18LF6310-I/PT Datasheet - Page 49

• Manufacturer Part Number: PIC18LF6310-I/PT
• Description: IC PIC MCU FLASH 4KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF6310-I/PT

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 54
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• No. Of Pwm: RoHS Compliant
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 3-2:
© 2007 Microchip Technology Inc.
Note 1:
Primary Device Clock
T1OSC or INTRC
2:
3:
4:
5:
(PRI_IDLE mode)
before Wake-up
Clock Source
(Sleep mode)
In this instance, refers specifically to the 31 kHz INTRC clock source.
T
with any other required delays (see Section 3.4 “Idle Modes”).
Includes both the INTOSC 8 MHz source and postscaler derived frequencies.
T
also designated as T
Execution continues during T
INTOSC
CSD
OST
None
is the Oscillator Start-up Timer (parameter 32). t
(parameter 38) is a required delay when waking from Sleep and all Idle modes and runs concurrently
EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
(3)
(1)
PLL
.
IOBST
EC, RC, INTRC
EC, RC, INTRC
EC, RC, INTRC
EC, RC, INTRC
after Wake-up
Clock Source
LP, XT, HS
INTOSC
LP, XT, HS
INTOSC
LP, XT, HS
INTOSC
LP, XT, HS
INTOSC
PIC18F6310/6410/8310/8410
(parameter 39), the INTOSC stabilization period.
HSPLL
HSPLL
HSPLL
HSPLL
Preliminary
(3)
(2)
(2)
(2)
(1)
(1)
(1)
(1)
rc
is the PLL Lock-out Timer (parameter F12); it is
T
T
T
Exit Delay
OST
OST
OST
T
T
T
T
T
T
T
T
T
IOBST
IOBST
None
CSD
OST
CSD
OST
CSD
OST
CSD
+ t
+ t
+ t
(2)
(4)
(2)
(5)
(2)
(4)
(2)
rc
rc
rc
(5)
(5)
(4)
(4)
(4)
Clock Ready Status
bit (OSCCON)
DS39635B-page 47
OSTS
OSTS
OSTS
OSTS
IOFS
IOFS
IOFS
IOFS
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