PIC18LF6310-I/PT Microchip Technology, PIC18LF6310-I/PT Datasheet - Page 379

• Manufacturer Part Number: PIC18LF6310-I/PT
• Description: IC PIC MCU FLASH 4KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF6310-I/PT

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 54
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• No. Of Pwm: RoHS Compliant
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FIGURE 26-23:
TABLE 26-26: A/D CONVERSION REQUIREMENTS
© 2007 Microchip Technology Inc.
130
131
132
135
TBD
Legend: TBD = To Be Determined
Note 1:
Param
No.
Note 1:
A/D DATA
SAMPLE
A/D CLK
2:
3:
4:
ADRES
BSF ADCON0, GO
T
T
T
T
T
Symbol
ADIF
AD
CNV
ACQ
SWC
DIS
2:
GO
Q4
The time of the A/D clock period is dependent on the device frequency and the T
ADRES register may be read on the following T
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (AV
50Ω.
On the following cycle of the device clock.
If the A/D clock source is selected as RC, a time of T
This allows the SLEEP instruction to be executed.
This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
132
A/D Clock Period
Conversion Time
(not including acquisition time) (Note 2)
Acquisition Time (Note 3)
Switching Time from Convert → Sample
Discharge Time
A/D CONVERSION TIMING
(Note 2)
Characteristic
9
DD
to AV
8
PIC18FXXXX
PIC18LFXXXX
PIC18FXXXX
PIC18LFXXXX
SS
PIC18F6310/6410/8310/8410
OLD_DATA
or AV
7
Preliminary
SS
. . .
SAMPLING STOPPED
CY
to AV
is added before the A/D clock starts.
CY
DD
. . .
131
130
cycle.
). The source impedance (R
TBD
TBD
TBD
TBD
Min
0.7
1.4
0.2
11
—
2
(Note 4)
25.0
TBD
TBD
TBD
Max
12
—
—
—
1
(1)
Units
T
μs
μs
μs
μs
μs
μs
μs
AD
0
T
V
T
A/D RC mode
V
A/D RC mode
-40°C to +85°C
0°C ≤ to ≤ +85°C
OSC
OSC
DD
DD
S
AD
) on the input channels is
= 2.0V;
= 2.0V;
based, V
based, V
clock divider.
NEW_DATA
DONE
Conditions
DS39635B-page 377
T
CY
REF
REF
≥ 3.0V
full range