PIC18LF6310-I/PT Microchip Technology, PIC18LF6310-I/PT Datasheet - Page 131

• Manufacturer Part Number: PIC18LF6310-I/PT
• Description: IC PIC MCU FLASH 4KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF6310-I/PT

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 54
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• No. Of Pwm: RoHS Compliant
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.5
PORTE is an 8-bit wide, bidirectional port. The
corresponding data direction register is TRISE. Setting
a TRISE bit (= 1) will make the corresponding PORTE
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISE bit (= 0)
will make the corresponding PORTE pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Output Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register read and write the latched output value for
PORTE.
All pins on PORTE are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
When the device is operating in Microcontroller mode,
pin RE7 can be configured as the alternate peripheral
pin for the CCP2 module. This is done by clearing the
CCP2MX Configuration bit.
In 80-pin devices, PORTE is multiplexed with the
system bus as part of the external memory interface.
I/O port and other functions are only available when the
interface is disabled by setting the EBDIS bit
(MEMCON<7>). When the interface is enabled (80-pin
devices only), PORTE is the high-order byte of the
multiplexed address/data bus (AD15:AD8). The TRISE
bits are also overridden.
© 2007 Microchip Technology Inc.
Note:
PORTE, TRISE and
LATE Registers
On a Power-on Reset, these pins are
configured as digital inputs.
PIC18F6310/6410/8310/8410
Preliminary
When the Parallel Slave Port is active on PORTD, three
of the PORTE pins (RE0/AD8/RD, RE1/AD9/WR and
RE2/AD10/CS) are configured as digital control inputs
for the port. The control functions are summarized in
Table 10-9. The reconfiguration occurs automatically
when the PSPMODE control bit (PSPCON<4>) is set.
Users must still make certain the corresponding TRISE
bits are set to configure these pins as digital inputs.
EXAMPLE 10-5:
CLRF
CLRF
MOVLW
MOVWF
PORTE
LATE
03h
TRISE
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RE<1:0> as inputs
; RE<7:2> as outputs
INITIALIZING PORTE
DS39635B-page 129